pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 315

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
2.1.1 The Start Mode
2.1.2 Warm Start
2.1 Start and Warm Start
There are two different start modes for the DDR SDRAM Controller: start, and the
warm start. MMIO register IP_2031_CTL provides the interface to start the DDR
controller.
The START field of MMIO register IP_2031_CTL is used to trigger the start mode of
the DDR SDRAM Controller. This mode is the common start mode. It is used when
neither the DDR controller nor the DDR devices are yet initialized. This is the normal
condition after a system reset has occurred. The MMIO registers that determine the
timing and characteristics of the DDR memories should be programmed prior to the
start action is triggered, since these register values may be used to configure the
external DDR memories. The normal sequence of actions to start the DDR controller
is to program the MMIO registers that configure the different parameters of the DDR
memory devices and then set the START field of MMIO register IP_2031_CTL to ‘1’.
This mode is used by the boot scripts.
Sequence of Actions During the Start Mode
During start (not warm start), the DDR SDRAM Controller performs the following
sequence of actions:
The Warm start mode is a special mode where the DDR controller initializes itself but
does not initialize the DDR devices. This mode is used in applications where the
power of the PNX15xx Series is shutdown after the DDR devices have been sent to
self-refresh mode. In that state the DDR devices remained powered and therefore
they retain the data and the configuration. Once the PNX15xx Series power supplies
are back on and an external reset is applied, the DDR controller can be started by
asserting the WARM_START field of MMIO register IP_2031_CTL. By doing so the
DDR controller configures itself without configuring the DDR devices. Instead the
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Apply a NOP command
Precharge all command
Load extended mode register
Load mode register, with DLL reset
256 cycles delay for DDL.
Precharge all command
Auto refresh command
Auto refresh command
Load mode register, with DLL reset deactivated
256 cycles delay
Rev. 3 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
9-2