pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 339

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 9: Register Description
PNX15XX_SER_3
Product data sheet
Bit
2
1
0
Offset 0x06 5004
Note: Addressing modes 2048_MODE, 1024_MODE, and the interleaving mode defined by the BANK_SWITCH field are
mutually exclusive. Setting 2048_MODE to ‘1’ sets the IP_2031 into 2048 byte stride mode, and makes the values of
1024_MODE and BANK_SWITCH “don’t cares” for the IP_2031. When 2048_MODE is ‘0’ and 1024_MODE is ‘1’, the
IP_2031 is set into 1024 byte stride mode, which makes the value of BANK_SWITCH a “don’t care” for the IP_2031.
31:4
3:0
Offset 0x06 5008
31
30:0
The address locations of the DDR memory ranks are determined by registers RANK0_ADDR_LO, RANK0_ADDR_HI, and
RANK1_ADDR_HI. Addresses in [RANK0_ADDR_LO, RANK0_ADDR_HI] are directed to rank 0, addresses in
[RANK0_ADDR_HI, RANK1_ADDR_HI] are directed to rank 1. Addresses outside the two ranks are said to cause an
address error.
Offset 0x06 5010
31:0
Offset 0x06 5014
31:0
Offset 0x06 5018
31:0
Dimension of DDR Memories
Offset 0x06 5080
31:13
Symbol
DDR_HALVE_WIDTH
SPEC_AUTO_PR
START
Unused
BANK_SWITCH
PON
LIMIT
ADDR_LO
ADDR_HI
ADDR_HI
Unused
DDR_DEF_BANK_SWITCH
AUTO_HALT_LIMIT
RANK0_ADDR_LO
RANK0_ADDR_HI
RANK1_ADDR_HI
DDR_MR
Access Value
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
0
-
3
0
-
0x0000
0000
0xFFFF
FFFF
0xFFFF
FFFF
-
Rev. 3 — 17 March 2006
Description
‘0’: The complete “dq” bus of the DDR interface is used.
‘1’: Only the lower halve of the data bus of the DDR interface is
used. Only DDR data bits “MM_DATA[15:0]” are in use.
‘0’: Speculative auto precharge is off.
‘1’: Speculative auto precharge is on.
‘1’: Start DDR controller. When started, controller will return the
start bit to ‘0’.
These bits should be ignored when read and written as 0s.
Switch banks every 2^BANK_SWITCH columns (each column has
a width of 4 bytes). For 32-byte interleaving set this value equal to
0x3. For full page/row interleaving set this value equal to the column
width value. Only the following values are supported:
0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, and 0xb.
Recommended value is 3.
Controls PON signal of the SSTL_2 PADs:
‘1’: May be set to ‘1’ when the DDR devices are sent into self-
refresh mode, i.e. after a HALT command.
‘0’: Normal operation: must be set back to ‘0’ before enabling again
the DDR devices, i.e. before the UNHALT command.
After LIMIT amount of IP_2031 idle cycles, automatic halt kicks in.
Address at which the DDR rank 0 address space starts.
Address at which the DDR rank 0 address space ends.
Address at which the DDR rank 1 address space ends.
These bits should be ignored when read, and written as 0’s.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
9-26