pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 325

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
2.3.2 DDR Memory Rank Locations
Table 4: Mapping scheme: 1024-Byte Interleaving, 256 Columns
Table 5: 1024-Byte Interleaving, 512 Columns
The DDR SDRAM Controller supports two DDR memory ranks. The location of these
two memory ranks in the MTL address space is defined by means of MMIO registers
RANK0_ADDR_LO, RANK0_ADDR_HI, and RANK1_ADDR_HI. Rank 1 starts where
rank0 leaves off in the MTL address space; i.e. the ranks are successive.
Programming of these MMIO registers should be consistent with the size of the
memories. An attempt to address an address outside of the two DDR memory ranks
will result in an error, which is registered by MMIO registers. Erroneous addressing
will still result in DDR read or write operations being performed.
Rank 1 starts where rank0 leaves off in the MTL address space i.e., the ranks are
successive. Programming these MMIO registers should be consistent with the
memory size. An attempt to address an address outside of the two DDR memory
ranks will result in an error, which is registered by MMIO registers. Erroneous
addressing will still result in DDR read or write operations being performed.
The start addresses of the ranks should be a multiple of the respective rank sizes.
The following examples will illustrate rank addressing and error detection situations.
MTL Address Range
0x000:0800-0x000:081f
0x000:0c00-0x000:0c1f
0x000:1000-0x000:101f
0x000:1400-0x000:141f
0x000:2000-0x000:201f
0x000:2400-0x000:241f
MTL Address Range
0x000:0000-0x000:001f
0x000:0020-0x000:003f
0x000:0040-0x000:005f
0x000:0060-0x000:007f
0x000:0400-0x000:041f
0x000:0800-0x000:081f
0x000:0c00-0x000:0c1f
0x000:1000-0x000:101f
0x000:1400-0x000:141f
0x000:2000-0x000:201f
0x000:2400-0x000:241f
Rev. 3 — 17 March 2006
Row Address
0x0000
0x0000
0x0001
0x0001
0x0002
0x0002
Row Address
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0001
0x0001
Bank Address
0b10
0b11
0b00
0b01
0b00
0b01
Bank Address
0b00
0b00
0b00
0b00
0b00
0b01
0b01
0b10
0b10
0b00
0b00
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
…Continued
Column Address
0x0000-0x0007
0x0000-0x0007
0x0000-0x0007
0x0000-0x0007
0x0000-0x0007
0x0000-0x0007
Column Address
0x0000-0x0007
0x0008-0x000f
0x0010-0x0017
0x0018-0x001f
0x0100-0x0107
0x0000-0x0007
0x0100-0x0107
0x0000-0x0007
0x0100-0x0107
0x0000-0x0007
0x0100-0x0107
9-12