pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 225

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 3: Recommended Settings for NAND
[1]
PNX15XX_SER_3
Product data sheet
Description
Read Data
Read ID
Read Status
Write Data
Block Erase
Reset
64-MB devices will require more address phases than shown..
Cmd
No.
1
1
1
2
2
1
Addr
No.
3
1
0
3
2
0
[1]
[1]
[1]
(address bits [24:17]), data, second command. For transactions with fewer than three
address phases, low address is first dropped, then middle address. Any transaction
that includes an address phase must include at least one command phase.
With a direct access to the NAND, n is limited to 4 bytes. Using the DMA, n is limited
to the segment length, 512 or 528 bytes with spare area. This is to allow time for the
busy signal to become stable at segment boundaries. The DMA may be programmed
to read much larger areas if the NAND does not assert its busy state or is allowed to
pause at segment boundaries. Programmers should consult the vendor’s data sheet
for the appropriate NAND-Flash selection.
The WEN and REN timing information will also be found in the data sheets. The
Document title variable module supports read profiles with low time from 1 to 4 PCI
clock periods. Write profiles of 1 to 4 PCI clock periods is supported for command
and address writes. Data writes must use a high time of at least 2 PCI clock periods.
If data is not part of the transaction, the second command will follow the last address
phase.
The ACK signal is monitored, when enabled, only at predetermined parts of the
transaction. During read operations, it will monitor the ACK after the last address
phase, before the read begins. The fixed delay must be programmed to a value
sufficient to allow the ACK to become valid before sampling it. This should include
time to double synchronize the ACK to the PCI clock. The ACK is also sampled
before starting a NAND transaction (but after the PCI wrapper has started). This
applies to all types of transactions. Even a status read will stall until the device is
ready if monitor ACK is enabled when starting the NAND transaction.
The read data operation may be done by blending DMA and direct access to
minimize the time the PCI bus is blocked from other types of transactions. To do this,
set the profile to issue 1 command, 3 address phase, and no data. Also load the
appropriate command into the Command A register. Next do a write to the starting
address of interest. Change the profile to 0 command, 0 address, include data. The
DMA should be programmed to transfer the selected amount of data to SDRAM. If
the DMA is started before the device is ready, it will stall until the device is ready.
Include
Data
Y
Y
Y
Y
N
N
Monitor
ACK
Y
N
N
Y
Y
N
Rev. 3 — 17 March 2006
Cmd A
00h or 01h
90h
70h
80h
60h
ffh
Cmd B
NA
NA
NA
10h
d0h
NA
Notes
Recommended to use DMA. This may be
set to more than one segment if
restricting max_burst_size to 128.
Recommended to use direct (or indirect)
access.
May read up to four bytes of status with
direct access.
Recommended to use DMA.
Recommended to use direct (or indirect)
access.
Recommended to use direct (or indirect)
access.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX15xx Series
7-6