pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 496

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 6:
must be low 1 clock
cycle before going active
must be high 1 clock
cycle before going active
Signal Edge Definition
clk
clk
3.1.2 Interrupt Service Routines
3.1.3 Optimized DMA Transfers
3.1.4 Terminating DMA Transfers
3.1.5 Signal Edge Definitions
Software must update the FGPI_BASEn register (where n is the number of the buffer
that interrupted with a buffer full interrupt) BEFORE clearing the buffer full interrupt
flag. This must be done even if the base address of the buffer does not change.
The DDR Memory controller used in the PNX15xx Series is optimized for 128-byte
block transfers on 128-byte address boundaries. To keep Main Memory bus traffic at
a minimum the programmer should program the FGPI_BASE1 and FGPI_BASE2
with bits [6:0] = 0000000 and program the FGPI_STRIDE to multiples of 128.
During the next-to-last BUFnFULL interrupt service routine turn off (set to ‘0’) the
associated FGPI_CTL.CAPTURE_ENABLE_n bit.
During the last BUFnFULL interrupt service routine turn off (set to ‘0’) the associated
FGPI_CTL.CAPTURE_ENABLE_n bit, the FGPI is now IDLE.
The FGPI uses only the rising edge of clk_fgpi. If the negative edge of an external
clock needs to be used, program the PNX15xx Series clock module to invert the
external clock for the FGPI.
sample point
sample point
(for pins: fgpi_start, fgpi_rec_start, fgpi_stop, fgpi_buf_start)
Rev. 3 — 17 March 2006
RISING EDGE
FALLING EDGE
Chapter 14: FGPI: Fast General Purpose Interface
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
14-13