pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 463

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 1:
Figure 2:
MMIO Bus
Top Level Block Diagram
DTL
Data
INITIATOR
DTL
Header
INITIATOR
FGPO Module Block Diagram
VDO Pads
32
DTL
MMIO
I/F
1.1 FGPO Overview
Figure 1
Busses within the PNX15xx Series. All external FGPO signals are registered and
routed through the Output Router module before leaving the PNX15xx Series.
Latency buffering of data and endian conversion is done in the MTL DTL Adapter. All
FGPO register access is through the MMIO DTL adapter.
Figure 2
Output Router
Clock Block
shows the top level connection of the FGPO module to the MMIO and MTL
shows the basic sections of the FGPO module.
DMA
ENGINE
32
Rev. 3 — 17 March 2006
fgpo_rec_sync
32
fgpo_buf_sync
Timestamp
FIFO
Chapter 13: FGPO: Fast General Purpose Output
32
32
Data
Output
Engine
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
8/16/32
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fgpo_stop
fgpo_data
MTL Bus
fgpo_start
13-2