pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 159

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 2:
extracted
for DFT
PLL Block Diagram
clk_in
(xtal_clk)
2.2.1 PLL Specification
Fin
100MHz F
A PLL consists of a Voltage Controlled Oscillator (VCO) and a Post Divide (PD)
circuit, as presented in
The frequency from the VCO, F
F
The bit width of N, M, P is 9, 5 and 2 bits respectively. The N, M and P bits are
programmable register bits in the Clock module control registers, PLL0_CTL and
PLL1_CTL. PLL2_CTL does not allow to control the P parameter since it is fixed to
‘1’, i.e. divides F
interface.
Remark: Using a value of 0 for either M or N could lead to undesirable behavior. For
that reason, setting either M or N to 0 will result in a value of 1 being used for both M
and N. Assuming the P value is set to 0, this will result in a PLL output frequency of 27
MHz.
PLL Limitations
The following equations must be met
General Recommendations
F
F
2MHz F
2MHz F
/M
VCO
VCO
out
•
5
Keep M with low values
=
Fpd
can be post divided by 1, 2, 4 and 8 according to the following equation:
=
F
---------- -
2
vco
27MHz
P
in
pd
vco
PD
150MHz
27MHz
600MHz
VCO
---- -
M
N
Rev. 3 — 17 March 2006
by 2, to ensure a 50% duty cycle clock on the DDR SDRAM
Figure
FILTER
PLL
LOOP
/N
2.
VCO
9
can be determined as follows:
VCO
Fvco
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
/P
2
Fout
clk_out
(1)
(2)
(3)
(4)
(5)
5-8