W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 108

• Manufacturer Part Number: W83977G
• Description: W83877TF plus KBC, CIR, RTC, Pb-free
• Manufacturer: Winbond Electronics Corp America

PERIODIC INTERRUPT RATE TABLE
9.3.2
SET
When the SET bit is set, any occurring update cycle is aborted and registers (Register 00h~09h,
Register (40h~48h) may be modified without entering an update cycle. When this bit is cleared, the
update cycle function occurs once per second. This bit is not affected by any other internal functions
or by a RESET.
PE
A "1" on the periodic interrupt enable bit enables the periodic interrupt flag (PF) bit in Register 0Ch to
assert an interrupt.
A "0" on this bit blocks the IRQ output from being driven by a periodic interrupt. This bit can not be
modified by any internal function, but it may be cleared by a RESET.
AE
A "1" on the enable bit of alarm A enables the alarm A flag (AF) bit in Register 0Ch to assert an
A "0" on this bit prohibits alarm A interrupt. The RESET signal clears AE to "0". This bit can not be
modified by any internal function.
NAME
BIT
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
interrupt.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Register 0Bh (Read/Write)
RS[3:0]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SET
7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PE
6
AE
5
-100
UE
4
122.070 μ S / 8.192KHz
244.141 μ S / 4.096KHz
488.281 μ S / 2.048KHz
976.562 μ S / 1.024KHz
1.953125mS / 512Hz
Reserved
3.90625mS / 256Hz
3.90625mS / 256Hz
7.8125mS / 128Hz
7.8125mS / 128Hz
15.625ms / 64Hz
31.25ms / 32Hz
62.5ms / 16Hz
125ms / 8Hz
250ms / 4Hz
500ms / 2Hz
3
TIME BASE
None
DM
2
12/24
1
DSE
0