W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 74

• Manufacturer Part Number: W83977G
• Description: W83877TF plus KBC, CIR, RTC, Pb-free
• Manufacturer: Winbond Electronics Corp America

These are combined to be a 13-bit register. Writing these registers programs the transmitter frame
length of a package.
Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame
length if the transmitted data is larger than the programmed frame length. When these registers are
read, they will return the number of bytes which is not transmitted from a frame length programmed.
7.6.5
These are combined to be a 13-bit registers and up counter. The length of receiver frame will be
limited to the programmed frame length. If the received frame length is larger than the programmed
receiver frame length, the bit of MX_LEX (Maximum Length Exceed) will be set to 1. Simultaneously,
the receiver will not receive any more data to RX FIFO until the next start flag of the next frame, which
is defined in the physical layer IrDA 1.1. Reading these registers returns the number of received data
bytes of a frame from the receiver.
7.7
7.7.1
If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed
baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL).
RFRLL
RFRLH
REG.
Reset
Value
Reset
Value
ADDRESS
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
OFFSET
Set 5 - Flow control and IR control and Frame Status FIFO registers
0
1
2
3
4
5
6
7
Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH)
Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
BIT 7
bit 7
0
-
-
REGISTER
RFRLFH
RFRLFL
IRCFG1
FCBHL
FC_MD
FCBLL
FS_FO
NAME
These registers are only valid when APM=1 (automatic package mode,
BIT 6
SSR
bit 6
0
-
-
Flow Control Baud Rate Divisor Latch Register (Low Byte)
Flow Control Baud Rate Divisor Latch Register (High Byte)
Flow Control Mode Operation
Sets Select Register
Infrared Configure Register
Frame Status FIFO Register
Receiver Frame Length FIFO Low Byte
Receiver Frame Length FIFO High Byte
BIT 5
bit 5
0
-
-
BIT 4
bit 12
bit 4
-66
0
0
REGISTER DESCRIPTION
BIT 3
bit 11
bit 3
0
0
BIT 2
bit 10
bit 2
0
0
BIT 1
bit 1
bit 9
0
0
BIT 0
bit 0
bit 8
0
0