W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 61

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W83977G

Manufacturer Part Number
W83977G
Description
W83877TF plus KBC, CIR, RTC, Pb-free
Manufacturer
Winbond Electronics Corp America
Datasheet

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Bit 2:
Bit 1:
Bit 0:
7.2.3.2
Legacy IR:
This register is used to control FIFO functions of the IR.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
TABLE: FIFO TRIGGER LEVEL
Advanced IR
Reset Value
Legacy IR
MODE
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
BIT 7
the interrupt active level is set as 4 bytes and there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify CPU to read the data from FIFO.
0
0
1
1
Advanced SIR/ASK-IR modes:
MIR, FIR modes:
Remote Controller Mode: Not used.
IR FIFO Control Register (UFR):
USR_I - IR Status Interrupt.
Set to 1 when overrun error, parity error, stop bit error, or silent byte error detected and
registered in the IR Status Register (USR). Cleared to 0 when USR is read.
FEND_I - Frame End Interrupt.
Set to 1 when (1) a frame has a grace end to be detected where the frame signal is
defined in the physical layer of IrDA version 1.1; (2) abort signal or illegal signal has been
detected during receiving valid data. Cleared to 0 when this register is read.
TXEMP_I - Transmitter Empty.
Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Cleared to 0 when this
register is read.
RXTH_I - Receiver Threshold Interrupt.
Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold
level; or (2) RBR time-out occurs if the receiver buffer register has valid data and below
the threshold level. Cleared to 0 when RBR is less than threshold level after reading
RBR.
RXFTL1
RXFTL1
(MSB)
(MSB)
BIT 7
0
BIT 6
0
1
0
1
RXFTL0 (LSB)
RXFTL0 (LSB) TXFTL1
BIT 6
0
(MSB)
BIT 5
0
0
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
-53 -
TXFTL0
BIT 4
(LSB)
0
0
BIT 3
0
0
0
01
04
08
14
Publication Release Date: May 2006
TXF_RST RXF_RST EN_FIFO
TXF_RST RXF_RST EN_FIFO
BIT 2
0
BIT 1
0
Revision 0.60
BIT 0
0

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