W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 76

• Manufacturer Part Number: W83977G
• Description: W83877TF plus KBC, CIR, RTC, Pb-free
• Manufacturer: Winbond Electronics Corp America

7.7.3
Writing this register selects Register Set. Reading this register returns ECH.
7.7.4
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3~2:
Bit 1:
Bit 0:
Default Value
IRCFG1
REG.
Reset
Value
REG.
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
SSR
Set5.Reg3 - Sets Select Register (SSR)
Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)
FSF_TH
Reserved, write 0.
FSF_TH - Frame Status FIFO Threshold
Set this bit to determine the frame status FIFO threshold level and to generate the FSF_I.
The threshold level values are defined as follows.
FEND_MD - Frame End Mode
A write to 1 enables hardware to split data stream into equal length frame automatically
as defined in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Reserved, write 0.
IRHSSL - Infrared Handshake Status Select
When set to 0, the HSR (Handshake Status Register) operates as same as defined in IR
mode. A write to 1 will disable HSR, and reading HSR returns 30H.
IR_FULL - Infrared Full Duplex Operation
When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate
in full duplex.
BIT 7
0
1
0
-
BIT 7
SSR7
1
FSF_TH
BIT 6
0
BIT 6
SSR6
1
FEND_M
BIT 5
0
SSR5
BIT 5
1
AUX_RX
BIT 4
-68
STATUS FIFO THRESHOLD LEVEL
SSR4
BIT 4
0
0
BIT 3
BIT 3
SSR3
0
-
1
2
4
BIT 2
BIT 2
SSR2
0
-
1
IRHSSL
BIT 1
SRR1
BIT 1
0
0
IR_FULL
SRR0
BIT 0
BIT 0
0
0