W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 60

• Manufacturer Part Number: W83977G
• Description: W83877TF plus KBC, CIR, RTC, Pb-free
• Manufacturer: Winbond Electronics Corp America

TABLE: INTERRUPT CONTROL FUNCTION
** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1.
Advanced IR:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 3
0
0
0
1
0
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
Bit 2
0
1
1
1
0
MIR, FIR modes:
Advanced SIR/ASK-IR, Remote IR modes: Not used.
MIR, FIR, Remote IR Modes:
ISR
DMA_I - DMA Interrupt.
Set to 1 if the DMA controller 8237A sends a TC (Terminal Count) to I/O device which
might be a Transmitter TC or a Receiver TC. Cleared to 0 when this register is read.
HS_I - Handshake Status Interrupt.
Set to 1 when the Handshake Status Register has a toggle.
Handshake Status Register (HSR) is read. Note that in all IR modes including SIR, ASK-
IR, MIR, FIR, and Remote Control IR, this bit defaults to be inactive unless IR Handshake
Status Enable (IRHS_EN) is set to 1.
TMR_I - Timer Interrupt.
Set to 1 when timer count to logical 0. This bit is valid when: (1) the timer registers are
defined in Set4.Reg0 and Set4.Reg1; (2) EN_TMR(Enable Timer, in Set4.Reg2.Bit0) is
set to 1; (3) ENTMR_I (Enable Timer Interrupt, in Set0.Reg1.Bit7) is set to 1.
FSF_I - Frame Status FIFO Interrupt.
Set to 1 when Frame Status FIFO is equal or larger than the threshold level or Frame
Status FIFO time-out occurs.
threshold level.
TXTH_I - Transmitter Threshold Interrupt.
Set to 1 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level.
Cleared to 0 if the TBR (Transmitter Buffer Register) FIFO is above the threshold level.
Bit 1
0
1
0
0
1
Bit 0
1
0
0
0
0
Interrupt
priority
First
Second
Second
Third
-
Interrupt Type
IR Receive
Status
RBR Data
Ready
FIFO Data
Time-out
TBR Empty
-
Cleared to 0 when Frame Status FIFO is below the
INTERRUPT SET AND FUNCTION
-52
Interrupt Source
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active
level reached
Data present in RX FIFO
for 4 characters period of
time since last access of
RX FIFO.
TBR empty
2. PBER =1
Clear Interrupt
Read USR
1. Read RBR
2. Read RBR until
FIFO
active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority
is third)
Cleared to 0 when
data under
-