W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 86

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W83977G

Manufacturer Part Number
W83977G
Description
W83877TF plus KBC, CIR, RTC, Pb-free
Manufacturer
Winbond Electronics Corp America
Datasheet

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Bit 7:
Bit 6~4:
Bit 3:
Bit 2~0:
7.9.6
Bit 7:
Bit 6~4:
Bit 3:
Bit 2~0:
7.9.7
Default Value
Default Value
IRM_SL2
IRM_SL3
REG.
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
REG.
Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2)
Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3)
IR_MSP - IR Mode Select Pulse
When set to 1, the transmitter (IRTX) will send a 64
end operational mode.
transmitter IR pulse (IRTX) to switch between high speed IR (such as FIR or MIR) and
low speed IR (SIR or ASK-IR), this bit should be used.
SIR_SL2~0 - SIR (Serial IR) mode select.
These bits are used to program the operational mode of the SIR front-end module.
These values of SIR_SL2~0 will be automatically loaded to pins of IR_SL2~0,
respectively, when (1) AM_FMT=1 (Automatic Format, in Set7.Reg7.Bit7); (2) the mode
of Advanced IR is set to SIR (AD_MD2~0, in Set0.Reg4.Bit7~0).
Reserved, write 0.
AIR_SL2~0 - ASK-IR Mode Select.
These bits setup the operational mode of ASK-IR front-end module when AM_FMT=1 and
AD_MD2~0 are configured to ASK-IR mode. These values will be automatically loaded to
IR_SL2~0, respectively.
Reserved, write 0.
FIR_SL2~0 - FIR mode select.
These bits setup the operational mode of FIR front-end module when AM_FMT=1 and
AD_MD2~0 are configured to FIR mode. These values will be automatically loaded to
IR_SL2~0, respectively.
Reserved, write 0.
MIR_SL2~0 - MIR Mode Select.
These bits setup the MIR operational mode when AM_FMT=1 and AD_MD2~0 are
configured to MIR mode.
respectively.
BIT 7
BIT 7
0
0
-
-
LRC_SL2
FIR_SL2
BIT 6
BIT 6
0
0
LRC_SL1
FIR_SL1
When IR front-end module uses mode select pin (MD) and
BIT 5
BIT 5
0
0
These values will be automatically loaded to IR_SL2~0,
LRC_SL0
FIR_SL0
-78
BIT 4
BIT 4
0
0
BIT 3
BIT 3
0
0
-
-
μ
s pulse to setup a special IR front-
HRC_SL2 HRC_SL1 HRC_SL0
MIR_SL2
BIT 2
BIT 2
0
0
MIR_SL1
BIT 1
BIT 1
0
0
MIR_SL0
BIT 0
BIT 0
0
0

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