W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 14

no-image

W83977G

Manufacturer Part Number
W83977G
Description
W83877TF plus KBC, CIR, RTC, Pb-free
Manufacturer
Winbond Electronics Corp America
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W83977G-A
Manufacturer:
INFINEON
Quantity:
214
Part Number:
W83977G-A
Manufacturer:
Winbond
Quantity:
1 000
Part Number:
W83977G-A
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
4. PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.
I/O6t - TTL level bi-directional pin with 6 mA source-sink capability
I/O8t - TTL level bi-directional pin with 8 mA source-sink capability
I/O8 - CMOS level bi-directional pin with 8 mA source-sink capability
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12 - CMOS level bi-directional pin with 12 mA source-sink capability
I/O16u - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
I/OD16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-
up resistor
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt - TTL level input pin
INc - CMOS level input pin
INcu - CMOS level input pin with internal pull-up resitor
INcs - CMOS level Schmitt-triggered input pin
INts - TTL level Schmitt-triggered input pin
INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor
4.1
A0
A11-A14
A15
D0
D6
AEN
IOCHRDY
MR
IOR
IOW
SYMBOL
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
A10
D5
D7
Host Interface
109-114
116-117
74-84
86-89
PIN
105
106
107
108
118
91
I/O 12t
I/O 12t
OD 24
IN ts
IN ts
IN ts
I/O
IN t
IN t
IN t
IN t
System address bus bits 0-10
System address bus bits 11-14
System address bus bit 15
System data bus bits 0-5
System data bus bits 6-7
CPU I/O read signal
CPU I/O write signal
System address bus enable
In EPP Mode, this pin is the IO Channel Ready output to extend the
host read/write cycle.
Master Reset. Active high. MR is low during normal operations.
-6
FUNCTION

Related parts for W83977G