W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 77

• Manufacturer Part Number: W83977G
• Description: W83877TF plus KBC, CIR, RTC, Pb-free
• Manufacturer: Winbond Electronics Corp America

7.7.5
This register shows the bottom byte of frame status FIFO.
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
7.7.6
RFLFL/ LST_NU
FS_FO
REG.
Reset
Value
Reset Value
Reset Value
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
RFLFH
REG.
FSFDR - Frame Status FIFO Data Ready
Indicate that a data byte is valid in frame status FIFO bottom.
LST_FR - Lost Frame
Set to 1 when one or more frames have been lost.
Reserved.
MX_LEX - Maximum Frame Length Exceed
Set to 1 when incoming data exceeds programmed maximum frame length defined in
Set4.Reg6 and Set4.Reg7. This bit is in frame status FIFO bottom and is valid only when
FSFDR=1 (Frame Status FIFO Data Ready).
PHY_ERR - Physical Error
When receiving data, any physical layer error as defined in IrDA 1.1 will set this bit to 1.
This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO
Data Ready).
CRC_ERR - CRC Error
Set to 1 when receive a bad CRC in a frame. This CRC belongs to physical layer as defined
in IrDA 1.1. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame
Status FIFO Data Ready).
RX_OV - Received Data Overrun
Set to 1 when receiver FIFO overruns.
FSF_OV - Frame Status FIFO Overrun
Set to 1 When frame status FIFO overruns.
Set5.Reg5 - Frame Status FIFO Register (FS_FO)
Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame
Number (LST_NU)
FSFDR
BIT 7
0
BIT 7
Bit 7
0
0
-
LST_FR
BIT 6
0
BIT 6
Bit 6
0
0
-
BIT 5
0
-
BIT 5
Bit 5
0
0
-
-69 -
MX_LEX
BIT 4
0
BIT 4
Bit 12
Bit 4
0
0
PHY_ERR CRC_ERR
BIT 3
0
BIT 3
Bit 11
Bit 3
0
0
Publication Release Date: May 2006
BIT 2
0
BIT 2
Bit 10
Bit 2
0
0
RX_OV
BIT 1
BIT 1
Bit 1
Bit 9
0
0
0
Revision 0.60
FSF_OV
BIT 0
BIT 0
Bit 0
Bit 8
0
0
0