W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 59

• Manufacturer Part Number: W83977G
• Description: W83877TF plus KBC, CIR, RTC, Pb-free
• Manufacturer: Winbond Electronics Corp America

Bit 1:
Bit 0:
7.2.3
7.2.3.1
Legacy IR:
This register reflects the Legacy IR interrupt status, which is encoded by different interrupt sources
into 3 bits.
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logical 0.
Bit 3: When not in FIFO mode, this bit is always 0. In FIFO mode, both bit 3 and 2 are set to logical 1
Bit 2, 1: These bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
Advanced IR
Reset Value
Legacy IR
MODE
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
when a time-out interrupt is pending.
this bit will be set to logical 0.
Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)
Interrupt Status Register (Read Only)
EHSRI/ETXURI - Enable USR Interrupt or Enable Transmitter Underrun Interrupt
A write to 1 will enable USR interrupt or enable transmitter underrun interrupt.
ETBREI - Enable TBR (Transmitter Buffer Register) Empty Interrupt
A write to 1 will enable the transmitter buffer register empty interrupt.
ERBRI - Enable RBR (Receiver Buffer Register) Interrupt
A write to 1 will enable receiver buffer register interrupt.
FIFO Enable
TMR_I
B7
0
FIFO Enable
FSF_I
B6
0
TXTH_I
B5
0
1
-51 -
DMA_I
B4
0
0
HS_I
IID2
B3
0
Publication Release Date: May 2006
FEND_I
USR_I/
IID1
B2
0
TXEMP_I
IID0
B1
1
Revision 0.60
RXTH_I
B0
IP
0