W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 69

• Manufacturer Part Number: W83977G
• Description: W83877TF plus KBC, CIR, RTC, Pb-free
• Manufacturer: Winbond Electronics Corp America

Bit 1:
Bit 0:
7.4.3
Reading this register returns E0H. Writing a value selects Register Set.
7.4.4
Bit 7:
Bit 6:
Bit 5, 4:
Bit 3, 2:
Refault Value
Advanced IR
Reset Value
MODE
REG.
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
SSR
Reg3 - Sets Select Register (SSR)
Reg4 - Advanced IR Control Register 2 (ADCR2)
PR_DIV1~0
DMA_F - DMA Fairness
ADV_SL - Advanced Mode Select
A write to 1 selects advanced mode.
DIS_BACK - Disable Backward Operation
A write to 1 disables backward legacy IR mode. When operate in legacy SIR/ASK-IR
mode, this bit should be set to 1 to avoid backward operation.
Reserved, write 0.
PR_DIV1~0 - Pre-Divisor 1~0.
These bits select pre-divisor for external input clock 24M Hz. The clock goes through the
pre-divisor then input to baud rate divisor of IR.
RX_FSZ1~0 - Receiver FIFO Size 1~0
These bits setup receiver FIFO size when FIFO is enable.
00
01
10
11
DIS_BACK
BIT 7
SSR7
BIT 7
1
0
DMA_F
0
1
BIT 6
SSR6
BIT 6
1
0
-
PR_DIV1
SSR5
BIT 5
BIT 5
1
0
DMA request (DREQ) is forced inactive after 10.5us
PRE-DIVISOR
-61 -
1.625
PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1
13.0
SSR4
BIT 4
6.5
BIT 4
1
0
0
No effect DMA request.
Function Description
BIT 3
SSR3
BIT 3
0
0
Publication Release Date: May 2006
BIT 2
SSR2
BIT 2
0
0
MAX. BAUD RATE
115.2K bps
921.6K bps
230.4K bps
1.5M bps
SRR1
BIT 1
BIT 1
0
0
Revision 0.60
TXFSZ0
SRR0
BIT 0
BIT 0
0
0