W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 25

• Manufacturer Part Number: W83977G
• Description: W83877TF plus KBC, CIR, RTC, Pb-free
• Manufacturer: Winbond Electronics Corp America

5. FDC FUNCTIONAL DESCRIPTION
5.1
The floppy disk controller of the W83977F/G, W83977AF/AG integrates all of the logic required for
floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default
to compatible values. The FIFO provides better system performance in multi-master systems. The
digital data separator supports up to 2 M bits/sec data rate.
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
5.1.1
The interface consists of the standard asynchronous signals: RD , WR , A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
5.1.2
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and
DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage
of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with a FIFO. The data are based upon the following
formula:
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
W83977F/G and W83977AF/AG FDC
FIFO THRESHOLD
FIFO THRESHOLD
AT interface
FIFO (Data)
15 Byte
15 Byte
2 Byte
8 Byte
1 Byte
2 Byte
8 Byte
1 Byte
THRESHOLD # × (1/DATA/RATE) *8 - 1.5 μS = DELAY
2 × 16 μS - 1.5 μS = 30.5 μS
8 × 16 μS - 1.5 μS = 6.5 μS
15 × 16 μS - 1.5 μS = 238.5 μS
1 × 8 μS - 1.5 μS = 6.5 μS
2 × 8 μS - 1.5 μS = 14.5 μS
8 × 8 μS - 1.5 μS = 62.5 μS
15 × 8 μS - 1.5 μS = 118.5 μS
1 × 16 μS - 1.5 μS = 14.5 μS
Data Rate
Data Rate
MAXIMUM DELAY TO SERVICING AT 500K BPS
MAXIMUM DELAY TO SERVICING AT 1M BPS
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Publication Release Date: May 2006
Revision 0.60