W83977G Winbond Electronics Corp America, W83977G Datasheet - Page 65

• Manufacturer Part Number: W83977G
• Description: W83877TF plus KBC, CIR, RTC, Pb-free
• Manufacturer: Winbond Electronics Corp America

7.2.6
Legacy IR Register: These registers are defined the same as previous description.
Advanced IR Register:
Bit 7:
Bit 6, 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1, 0:
7.2.7
7.2.8
Legacy IR
Advanced
Advanced IR
Reset Value
MODE
Legacy IR
Reset
Value
MODE
IR
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
MIR, FIR Modes:
MIR, FIR modes:
MIR, FIR modes:
MIR, FIR Modes:
Set0.Reg5 - IR Status Register (USR)
Set0.Reg6 - Reserved
Set0.Reg7 - User Defined Register (UDR/AUDR)
LB_INFR - Last Byte In Frame End
Set to 1 when last byte of a frame is in the bottom of FIFO. This bit separates one frame
from another when RX FIFO has more than one frame.
Same as legacy IR description.
MX_LEX - Maximum Frame Length Exceed
Set to 1 when the length of a frame from the receiver has exceeded the programmed
frame length defined in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not
receive any data to RX FIFO.
PHY_ERR - Physical Layer Error
Set to 1 when an illegal data symbol is received. The illegal data symbol is defined in
physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will be
aborted and a frame end signal is set to 1.
CRC_ERR - CRC Error
Set to 1 when an attached CRC is erroneous.
OER - Overrun Error, RDR - RBR Data Ready
Definitions are the same as legacy IR.
FLC_ACT
BIT 7
Bit 7
LB_INFR
0
RFEI
B7
0
UNDRN
BIT 6
Bit 6
0
TSRE
TSRE
B6
0
RX_BSY/
RX_IP
BIT 5
Bit 5
TBRE
TBRE
0
B5
0
-57 -
LST_FE/
MX_LEX
RX_PD
BIT 4
Bit 4
SBD
B4
0
0
PHY_ERR CRC_ERR
S_FEND
NSER
BIT 3
Bit 3
B3
0
0
Publication Release Date: May 2006
BIT 2
PBER
Bit 2
B2
0
0
0
LB_SF
BIT 1
Bit 1
OER
OER
B1
0
0
Revision 0.60
RX_TO
BIT 0
RDR
Bit 0
RDR
B0
0
0