r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1007

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

The contents of the CPU remain unchanged. Some registers of on-chip peripheral modules are,
however, initialized. Regarding the states of on-chip peripheral module registers in software
standby mode, see section 24.3, Register States in Each Operating Mode.
The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next
instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP
instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely
reflected in the SLEEP instruction.
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate
3. After setting the STBY bit in STBCR to 1, read STBCR. Then, execute a SLEEP instruction.
(2)
Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (manual reset or power-
on reset). The CKIO pin starts outputting the clock in clock mode 2.
• Canceling with an interrupt
values to secure the specified oscillation settling time.
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling
edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits
(IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC))
is detected, clock oscillation is started. This clock pulse is supplied only to the oscillation
settling counter (WDT) used to count the oscillation settling time.
After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer
control/status register (WTCSR) of the WDT before the transition to software standby mode,
the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the
clock pulse will be supplied to the entire chip after this overflow. Software standby mode is
thus cleared and NMI interrupt exception handling (IRQ interrupt exception handling in the
case of IRQ) starts. However, if the priority level of IRQ interrupt is lower than the interrupt
mask level set in the status register (SR) of the CPU, the interrupt request is not accepted and
thus the software standby mode is not released.
When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the
CKS[2:0] bits so that the WDT overflow period will be equal to or longer than the oscillation
settling time.
Canceling Software Standby Mode
Rev. 2.00 Dec. 09, 2005 Page 983 of 1152
Section 22 Power-Down Modes
REJ09B0191-0200