r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 198

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 User Break Controller (UBC)
6.4.4
When a user break interrupt request is received, the address of the instruction from where
execution is to be resumed is saved to the stack, and the exception handling state is entered. If the
C bus (FAB)/instruction fetch cycle is specified as a break condition, the instruction at which the
break should occur can be uniquely determined. If the C bus/data access cycle or I bus/data access
cycle is specified as a break condition, the instruction at which the break should occur cannot be
uniquely determined.
1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break
2. When C bus (FAB)/instruction fetch (after instruction execution) is specified as a break
3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition:
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REJ09B0191-0200
condition:
The address of the instruction that matched the break condition is saved to the stack. The
instruction that matched the condition is not executed, and the break occurs before it. However
when a delay slot instruction matches the condition, the instruction is executed, and the branch
destination address is saved to the stack.
condition:
The address of the instruction following the instruction that matched the break condition is
saved to the stack. The instruction that matches the condition is executed, and the break occurs
before the next instruction is executed. However when a delayed branch instruction or delay
slot matches the condition, the instruction is executed, and the branch destination address is
saved to the stack.
The address after executing several instructions of the instruction that matched the break
condition is saved to the stack.
Value of Saved Program Counter