r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 92

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
(1)
In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset.
(2)
The exception handling state is a transient state that occurs when exception handling sources such
as resets or interrupts alter the CPU’s processing state flow.
For a reset, the initial values of the program counter (PC) (execution start address) and stack
pointer (SP) are fetched from the exception handling vector table and stored; the CPU then
branches to the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception handling vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
(3)
In the program execution state, the CPU sequentially executes the program.
(4)
In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP
instruction places the CPU in the sleep mode or the software standby mode.
(5)
In the bus-released state, the CPU releases bus to a device that has requested it.
Rev. 2.00 Dec. 09, 2005 Page 68 of 1152
REJ09B0191-0200
Reset State
Exception Handling State
Program Execution State
Power-Down State
Bus-Released State