r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 342

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 Bus State Controller (BSC)
(12) Power-On Sequence
In order to use SDRAM, mode setting must first be made for SDRAM after waiting for 100 µs or
a longer period after powering on. This 100-µs or longer period should be obtained by a power-on
reset generating circuit or software.
To perform SDRAM initialization correctly, the bus state controller registers must first be set,
followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address
signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL,
and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be
written to the SDRAM mode register by performing a write to address H'FFFC4000 + X for area 2
SDRAM, and to address H'FFFC5000 + X for area 3 SDRAM. In this operation the data is
ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS
latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is
written in a byte-size access to the addresses shown in table 8.15. In this time 0 is output at the
external address pins of A12 or later.
Table 8.15 Access Address in SDRAM Mode Register Write
• Setting for Area 2
Rev. 2.00 Dec. 09, 2005 Page 318 of 1152
REJ09B0191-0200
Data Bus Width
16 bits
32 bits
Data Bus Width
16 bits
32 bits
Burst read/single write (burst length 1):
Burst read/burst write (burst length 1):
CAS Latency
2
3
2
3
CAS Latency
2
3
2
3
Access Address
H'FFFC4440
H'FFFC4460
H'FFFC4880
H'FFFC48C0
Access Address
H'FFFC4040
H'FFFC4060
H'FFFC4080
H'FFFC40C0
External Address Pin
H'0000440
H'0000460
H'0000880
H'00008C0
External Address Pin
H'0000040
H'0000060
H'0000080
H'00000C0