r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 701

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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0
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
12.3.5
ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the
enable/disable of interrupts, and indicates status.
Initial value:
Bit
8
7 to 0
Bit
15 to 13 —
Notes:
R/W:
Bit:
2. Can be modified only once after a power-on reset.
1.
2.
Input Level Control/Status Register 3 (ICSR3)
Bit Name
Bit Name
OIE2
Only 0 can be written to clear the flag after 1 is read.
Can be modified only once after a power-on reset.
15
R
0
-
14
R
0
-
Initial
Value
0
All 0
Initial
Value
All 0
13
R
0
-
R/(W)*
POE8F
12
0
1
R/W
R/W
R
R/W
R
11
R
0
-
10
R
0
-
Description
Output Short Interrupt Enable 2
Enables or disables interrupt requests when the OSF2 bit
in OCSR2 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
POE8E
R/W*
9
0
2
R/W
PIE3
8
0
R
7
0
-
Rev. 2.00 Dec. 09, 2005 Page 677 of 1152
Section 12 Port Output Enable 2 (POE2)
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
REJ09B0191-0200
2
R
0
-
R/W*
POE8M[1:0]
1
0
2
R/W*
0
0
2

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