r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 107

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

3.5
The frequency of the internal clock (Iφ) and peripheral clock (Pφ) can be changed either by
changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All
of these are controlled by software through the frequency control register (FRQCR). The methods
are described below.
3.5.1
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-
chip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1 time.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
3. Set the desired value in the STC[2:0] bits. The division ratio can also be set in the IFC[2:0] and
4. This LSI pauses temporarily and the WDT starts incrementing. The internal and peripheral
5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins
WDT. The following must be set:
WTCSR.TME = 0: WDT stops
WTCSR.CKS[2:0]: Division ratio of WDT count clock
WTCNT counter: Initial counter value
(The WDT count is incremented using the clock after the setting.)
PFC[2:0] bits.
clocks both stop and the WDT is supplied with the clock. The clock will continue to be output
at the CKIO pin. This state is the same as software standby mode. Whether or not registers are
initialized depends on the module. For details, see section 24.3, Register States in Each
Operating Mode.
operating again. The WDT stops after it overflows.
Changing the Frequency
Changing the Multiplication Rate
Rev. 2.00 Dec. 09, 2005 Page 83 of 1152
Section 3 Clock Pulse Generator (CPG)
REJ09B0191-0200