r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 824

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
Rev. 2.00 Dec. 09, 2005 Page 800 of 1152
REJ09B0191-0200
Bit
2
1
0
Bit Name
AL/OVE
AAS
ADZ
2
C Bus Interface 3 (IIC3)
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Arbitration Lost Flag/Overrun Error Flag
Indicates that arbitration was lost in master mode with
the I
received while RDRF = 1 with the clocked synchronous
format.
When two or more master devices attempt to seize the
bus at nearly the same time, if the I
detects data differing from the data it sent, it sets AL to
1 to indicate that the bus has been occupied by another
master.
[Clearing condition]
•
[Setting conditions]
•
•
•
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first
frame following a start condition matches bits SVA[6:0]
in SAR.
[Clearing condition]
•
[Setting conditions]
•
•
General Call Address Recognition Flag
This bit is valid in slave receive mode with the I
format.
[Clearing condition]
•
[Setting condition]
•
When 0 is written in AL/OVE after reading AL/OVE
= 1
If the internal SDA and SDA pin disagree at the rise
of SCL in master transmit mode
When the SDA pin outputs high in master mode
while a start condition is detected
When the final bit is received with the clocked
synchronous format while RDRF = 1
When 0 is written in AAS after reading AAS = 1
When the slave address is detected in slave receive
mode
When the general call address is detected in slave
receive mode.
When 0 is written in ADZ after reading ADZ = 1
When the general call address is detected in slave
receive mode
2
C bus format and that the final bit has been
2
C bus interface 3
2
C bus