r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 60

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
2.3
2.3.1
Instructions are RISC type. This section details their functions.
(1)
Basic instructions have a fixed length of 16 bits, improving program code efficiency.
(2)
The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease
of use.
(3)
Each basic instruction can be executed in one cycle using the pipeline system.
(4)
Longword is the standard data length for all operations. Memory can be accessed in bytes, words,
or longwords. Byte or word data in memory is sign-extended and handled as longword data.
Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It
is also handled as longword data.
Table 2.2
Note: @(disp, PC) accesses the immediate data.
(5)
Basic operations are executed between registers. For operations that involve memory access, data
is loaded to the registers and executed (load-store architecture). Instructions such as AND that
manipulate bits, however, are executed directly in memory.
Rev. 2.00 Dec. 09, 2005 Page 36 of 1152
REJ09B0191-0200
SH2-A CPU
MOV.W
ADD
.DATA.W
16-Bit Fixed-Length Instructions
32-Bit Fixed-Length Instructions
One Instruction per State
Data Length
Load-Store Architecture
Instruction Features
RISC-Type Instruction Set
@(disp,PC),R1
R1,R0
.........
H'1234
Sign Extension of Word Data
Description
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
Example of Other CPU
ADD.W
#H'1234,R0