r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 114

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 4 Exception Handling
When exception handling starts, the CPU operates as follows:
(1)
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004
addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets).
See section 4.1.3, Exception Handling Vector Table, for more information. The vector base
register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the
status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN
bit in IBNR of the interrupt controller (INTC) is also initialized to 0. The program begins running
from the PC address fetched from the exception handling vector table.
(2)
SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling
other than NMI or user breaks with usage of the register banks enabled, general registers R0 to
R14, control register GBR, system registers MACH, MACL, and PR, and the vector table address
offset of the interrupt exception handling to be executed are saved to the register banks. In the case
of exception handling due to an address error, register bank error, NMI interrupt, user break
interrupt, or instruction, saving to a register bank is not performed. When saving is performed to
all register banks, automatic saving to the stack is performed instead of register bank saving. In
this case, an interrupt controller setting must have been made so that register bank overflow
exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept
register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is 1),
register bank overflow exception will be generated. In the case of interrupt exception handling, the
interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to
an address error or instruction, the I3 to I0 bits are not affected. The exception service routine start
address is then fetched from the exception handling vector table and the program begins running
from that address.
Rev. 2.00 Dec. 09, 2005 Page 90 of 1152
REJ09B0191-0200
Exception Handling Triggered by Reset
Exception Handling Triggered by Address Errors, Register Bank Errors, Interrupts,
and Instructions