r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 410

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Direct Memory Access Controller (DMAC)
Rev. 2.00 Dec. 09, 2005 Page 386 of 1152
REJ09B0191-0200
Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the
2. DREQ level detection in burst mode (external request) or cycle steal mode.
3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode.
DE and DME bits are set to 1.
When reload function is enabled,
the transfer acknowledge signal
(SAR, DAR, DMATCR, CHCR,
RSAR → SAR, RDAR → DAR,
and RDMATCR → DMATCR
DMATCR – 1 → DMATCR,
Transfer (one transfer unit);
on-chip peripheral module,
SAR and DAR updated
For a request from an
is sent to the module.
DEI interrupt request
or AE = 1 or DE = 0
NMIF, AE, TE = 0?
DMAOR, DMARS)
Initial settings
DE, DME = 1 and
Transfer request
DMATCR = 0?
(when IE = 1)
Transfer end
or DME = 0?
occurs?*
Yes
Yes
Yes
NMIF = 1
Yes
TE = 1
Start
1
Figure 9.2 DMA Transfer Flowchart
No
No
No
No
Normal end
for a request from an on-chip peripheral
When the TC bit in CHCR is 0, or
module, the transfer acknowledge
signal is sent to the module.
Yes
HEI interrupt request
or AE = 1 or DE = 0
Transfer terminated
DMATCR=1/2 ?
(when HE = 1)
or DME = 0?
Yes
NMIF = 1
HE=1
*
3
No
DREQ detection system
transfer request mode,
No
Bus mode,
*
2