MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 91
MC68HC711xxxx
Manufacturer Part Number
MC68HC711xxxx
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC711XXXX.pdf
(268 pages)
- Current page: 91 of 268
- Download datasheet (4Mb)
5.2.4 Clock Monitor Reset
M68HC11E Family — Rev. 5
MOTOROLA
Complete this 2-step reset sequence to service the COP timer:
Performing instructions between these two steps is possible as long
as both steps are completed in the correct sequence before the timer times out.
The clock monitor circuit is based on an internal resistor capacitor (RC) time delay.
If no MCU clock edges are detected within this RC time delay, the clock monitor
can optionally generate a system reset. The clock monitor function is enabled or
disabled by the CME control bit in the OPTION register. The presence of a timeout
is determined by the RC delay, which allows the clock monitor to operate without
any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the COP needs
a clock to function, it is disabled when the clock stops. Therefore, the clock monitor
system can detect clock failures not detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout values
between individual devices. An E-clock frequency below 10 kHz is detected as a
clock monitor error. An E-clock frequency of 200 kHz or more prevents clock
monitor errors. Using the clock monitor function when the E-clock is below 200 kHz
is not recommended.
Special considerations are needed when a STOP instruction is executed and the
clock monitor is enabled. Because the STOP function causes the clocks to be
halted, the clock monitor function generates a reset sequence if it is enabled at the
time the stop mode was initiated. Before executing a STOP instruction, clear the
CME bit in the OPTION register to 0 to disable the clock monitor. After recovery
from STOP, set the CME bit to logic 1 to enable the clock monitor. Alternatively,
executing a STOP instruction with the CME bit set to logic 1 can be used as a
software initiated reset.
1. Write $55 to COPRST to arm the COP timer clearing mechanism.
2. Write $AA to COPRST to clear the COP timer.
Address
Reset:
Read:
Write:
Figure 5-1. Arm/Reset COP Timer Circuitry Register (COPRST)
$103A
BIT 7
Bit 7
0
BIT 6
Resets and Interrupts
6
0
BIT 5
0
5
BIT 4
4
0
BIT 3
3
0
BIT 2
0
2
Resets and Interrupts
BIT 1
1
0
Data Sheet
BIT 0
Bit 0
Resets
0
91
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