MC68HC705BD3

Manufacturer Part NumberMC68HC705BD3
DescriptionHigh-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
ManufacturerFREESCALE [Freescale Semiconductor, Inc]
MC68HC705BD3 datasheet
 
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MC68HC05BD3D/H
HC05
MC68HC05BD3
MC68HC705BD3
MC68HC05BD5
TECHNICAL
DATA

MC68HC705BD3 Summary of contents

  • Page 1

    ... HC05 MC68HC05BD3 MC68HC705BD3 MC68HC05BD5 TECHNICAL DATA MC68HC05BD3D/H ...

  • Page 2

    ...

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    ... PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3 MC68HC05BD5 TPG ...

  • Page 4

    ... GENERAL DESCRIPTION 2 PIN DESCRIPTION AND I/O PORTS 3 MEMORY AND REGISTERS 4 RESETS AND INTERRUPTS 5 MULTI-FUNCTION TIMER 6 PULSE WIDTH MODULATION 7 M-BUS SERIAL INTERFACE 8 SYNC SIGNAL PROCESSOR 9 CPU CORE AND INSTRUCTION SET 10 LOW POWER MODES 11 OPERATING MODES 12 ELECTRICAL SPECIFICATIONS 13 MECHANICAL SPECIFICATIONS 14 MC68HC705BD3 15 MC68HC05BD5 TPG ...

  • Page 5

    ... MC68HC05BD3 MC68HC705BD3 MC68HC05BD5 High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit TPG ...

  • Page 6

    Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; ...

  • Page 7

    ... SECTION 10 LOW POWER MODES SECTION 11 OPERATING MODES SECTION 12 ELECTRICAL SPECIFICATIONS SECTION 13 MECHANICAL SPECIFICATIONS SECTION 14 MC68HC705BD3 SECTION 15 MC68HC05BD5 Comments: 6. Have you found any errors? If so, please comment: 7. From your point of view, is anything missing from the document? If so, please say what: Poor Excellent ...

  • Page 8

    How could we improve this document? 9. How would you rate Motorola’s documentation? – In general – Against other semiconductor suppliers 10. Which semiconductor manufacturer provides the best technical documentation? 11. Which company (in any field) provides the best ...

  • Page 9

    ... PIN DESCRIPTIONS.............................................................................................2-1 2.2 Pin Assignments ....................................................................................................2-2 2.3 INPUT/OUTPUT PORTS.......................................................................................2-3 2.3.1 Port A ...............................................................................................................2-3 2.3.2 Port B ...............................................................................................................2-3 2.3.3 Port C ...............................................................................................................2-4 2.3.4 Port D ...............................................................................................................2-4 2.3.5 Input/Output Programming...............................................................................2-4 2.3.6 Port C and D Configuration Registers..............................................................2-5 3.1 Registers ...............................................................................................................3-1 3.2 RAM (MC68HC05BD3)..........................................................................................3-1 3.3 RAM (MC68HC705BD3/MC68HC05BD5).............................................................3-1 3.4 ROM (MC68HC05BD3) .........................................................................................3-2 3.5 ROM (MC68HC05BD5) .........................................................................................3-2 3.6 EPROM (MC68HC705BD3) ..................................................................................3-2 3.7 Bootstrap ROM ......................................................................................................3-2 MC68HC05BD3 TITLE 1 GENERAL DESCRIPTION 2 3 MEMORY AND REGISTERS Page Number TPG i ...

  • Page 10

    Paragraph Number 4.1 RESETS ................................................................................................................4-1 4.1.1 Power-On Reset (POR) ...................................................................................4-1 4.1.2 RESET Pin.......................................................................................................4-1 4.1.3 Illegal Address (ILADR) Reset.........................................................................4-2 4.1.4 Computer Operating Properly (COP) Reset ....................................................4-2 4.2 INTERRUPTS........................................................................................................4-3 4.2.1 Non-maskable Software Interrupt (SWI) ..........................................................4-3 4.2.2 Maskable Hardware Interrupts.........................................................................4-5 4.2.2.1 External Interrupt ...

  • Page 11

    Paragraph Number 7.3.1 M-Bus Address Register (MADR) ....................................................................7-6 7.3.2 M-Bus Frequency Register (MFDR).................................................................7-6 7.3.3 M-Bus Control Register (MCR) ........................................................................7-7 7.3.4 M-Bus Status Register (MSR)..........................................................................7-8 7.3.5 M-Bus Data I/O Register (MDR) ......................................................................7-9 7.4 Programming Considerations ................................................................................7-11 7.4.1 Initialization ......................................................................................................7-11 7.4.2 Generation ...

  • Page 12

    Paragraph Number 9.2 Instruction set ........................................................................................................9-3 9.2.1 Register/memory Instructions ..........................................................................9-4 9.2.2 Branch instructions ..........................................................................................9-4 9.2.3 Bit manipulation instructions ............................................................................9-4 9.2.4 Read/modify/write instructions.........................................................................9-4 9.2.5 Control instructions ..........................................................................................9-4 9.2.6 Tables...............................................................................................................9-4 9.3 Addressing modes.................................................................................................9-11 9.3.1 Inherent............................................................................................................9-11 9.3.2 Immediate ........................................................................................................9-11 9.3.3 Direct ...............................................................................................................9-11 9.3.4 ...

  • Page 13

    ... Paragraph Number MECHANICAL SPECIFICATIONS 13.1 42-Pin SDIP Package (Case 858-01) ..................................................................13-1 13.2 40-Pin DIP Package (Case 711-03).....................................................................13-1 14.1 Features...............................................................................................................14-1 14.2 Memory Map........................................................................................................14-1 14.3 EPROM Programming .........................................................................................14-1 14.3.1 Programming Control Register (PCR)............................................................14-3 14.3.2 EPROM Programming Sequence ..................................................................14-3 14.4 DC Electrical Characteristics ...............................................................................14-4 15.1 Features...............................................................................................................15-1 15.2 Memory Map........................................................................................................15-1 15.3 DC Electrical Characteristics ...............................................................................15-3 MC68HC05BD3 TITLE 13 14 MC68HC705BD3 15 MC68HC05BD5 Page Number TPG v ...

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    THIS PAGE LEFT BLANK INTENTIONALLY vi TPG MC68HC05BD3 ...

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    ... LIST OF FIGURES Figure Number 1-1 MC68HC05BD3/MC68HC705BD3/MC68HC05BD5 Block Diagram ......................1-2 2-1 Pin Assignment for 40-pin DIP Package.................................................................2-2 2-2 Pin Assignment for 42-pin SDIP Package ..............................................................2-3 2-3 Parallel Port I/O Circuitry ........................................................................................2-6 3-1 Memory Map ..........................................................................................................3-3 4-1 Power-On Reset and RESET Timing......................................................................4-2 4-2 Interrupt Stacking Order .........................................................................................4-4 4-3 External Interrupt Circuit and Timing ......................................................................4-6 6-1 8-Bit PWM Output Waveforms................................................................................6-2 7-1 M-Bus Interface Block Diagram ...

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    THIS PAGE LEFT BLANK INTENTIONALLY viii TPG MC68HC05BD3 ...

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    ... Mode Selection.....................................................................................................11-2 11-2 Self-Check Report ................................................................................................11-4 12-1 DC Electrical Characteristics for MC68HC05BD3 ................................................12-2 12-2 Control Timing ......................................................................................................12-3 12-3 M-Bus Interface Input Signal Timing.....................................................................12-4 12-4 M-Bus Interface Output Signal Timing..................................................................12-4 12-5 Sync Signal Processor Timing..............................................................................12-5 14-1 MC68HC705BD3 Programming Boards...............................................................14-1 14-2 DC Electrical Characteristics for MC68HC705BD3 ..............................................14-4 15-1 DC Electrical Characteristics for MC68HC05BD5 ................................................15-3 MC68HC05BD3 LIST OF TABLES TITLE Page Number TPG ix ...

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    THIS PAGE LEFT BLANK INTENTIONALLY x TPG MC68HC05BD3 ...

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    ... The MC68HC705BD3 is an EPROM version of the MC68HC05BD5. All references to the MC68HC05BD3 apply equally to the MC68HC705BD3 and MC68HC05BD5, unless otherwise stated. References specific to the MC68HC705BD3 are italicized in the text and also, for quick reference, they are summarized in Section 14. References to MC68HC05BD5 are summarized in Section 15 ...

  • Page 20

    ... Available in 40-pin DIP and 42-pin SDIP packages 3.75K-Bytes for MC68HC05BD3 7.75K-Bytes for MC68HC05BD5 7.75K-Bytes EPROM for MC68HC705BD3 128 Bytes for MC68HC05BD3 RAM 256 Bytes for MC68HC705BD3 & MC68HC05BD5 SELF-CHECK ROM - 224 Bytes for MC68HC05BD3 & MC68HC05BD5 only BOOTSTRAP ROM - 480 Bytes for MC68HC705BD3 only M68HC05 ...

  • Page 21

    ... These options are negative edge-sensitive triggering only both negative edge-sensitive and level sensitive triggering. In the bootstrap mode on the MC68HC705BD3, this is the EPROM programming voltage input pin. The active low RESET input is not required for start-up, but can be 4 used to reset the MCU internal state and provide an orderly software start-up procedure ...

  • Page 22

    DIP PIN NAME PIN No. 2 PC6/PWM14/VTTL, 32, 33 PC7/PWM15/HTTL PD0/SDA, 24, 25 PD1/SCL PWM0 to PWM7 3-1, 38-34 HSYNC, VSYNC 39, 40 2.2 Pin Assignments Figure 2-1 Pin Assignment for 40-pin DIP Package 2-2 42-pin SDIP PIN No. ...

  • Page 23

    IRQ/ VPP Figure 2-2 Pin Assignment for 42-pin SDIP Package 2.3 INPUT/OUTPUT PORTS In the User Mode there are 24 bidirectional I/O lines arranged as 4 I/O ports (Port and D). The individual bits in these ports ...

  • Page 24

    Port C 2 Port 8-bit bidirectional port which shares pins with PWM and SSP subsystem. See Section 6 for a detailed description of PWM and Section 8 for a detailed description of SSP. These pins are ...

  • Page 25

    Port C and D Configuration Registers Port C and Port D are shared with PWM, M-Bus and SSP. The configuration registers at $0A and $0B are used to configure those I/O pins. They are default to zero after power-on ...

  • Page 26

    INTERNAL LATCHED OUTPUT MC68HC05 CONNECTIONS TYPICAL PORT DATA DIRECTION REGISTER TYPICAL PORT REGISTER I/O PORT LINES PORT DATA PORT DDR INTERNAL LOGIC 2-6 DATA DIRECTION REGISTER BIT DATA BIT INPUT REGISTER BIT INPUT I/O ( ...

  • Page 27

    ... MEMORY AND REGISTERS The MC68HC05BD3/MC68HC705BD3/MC68HC05BD5 has a 16K-byte memory map consisting of registers, user ROM/ EPROM , user RAM, self-check/ bootstrap ROM, and I/O as shown in Figure 3-1. 3.1 Registers All the I/O, control and status registers of the MC68HC05BD3 are contained within the first 48-byte block of the memory map (address $0000 to $002F). ...

  • Page 28

    ... The user ROM consists of 7.75K-bytes of memory, from $2000 to $3EFF. 3.6 EPROM (MC68HC705BD3) The user EPROM consists of 7.75K-bytes of memory, from $2000 to $3EFF. 3.7 Bootstrap ROM This is available on the MC68HC705BD3 device only. It stores the on-chip program for programming the user EPROM. 3-2 MEMORY AND REGISTERS TPG MC68HC05BD3 ...

  • Page 29

    ... Bytes $3FDF $3FDF $3FE0 $3FE0 Self-Check Self-Check Vectors 16 Bytes $3FEF $3FEF $3FF0 $3FF0 User Vectors User Vectors 16 Bytes $3FFF $3FFF MC68HC05BD3 MC68HC705BD3 $0000 I/O I/O 48 Bytes 48 Bytes $002F $0030 Unused Unused $007F $0080 $00C0 Stack 64 Bytes $00FF User RAM 256 Bytes $017F ...

  • Page 30

    Register Name Port A data Port B data Port C data Port D data Port A data direction Port B data direction Port C data direction Port D data direction MFT control and status MFT timer counter Configuration 1 ...

  • Page 31

    Register Name Address bit 7 0PWM $0020 0PWM4 0PWM3 0PWM2 0PWM1 0PWM0 0BRM2 0BRM1 0BRM0 0000 0000 1PWM $0021 1PWM4 1PWM3 1PWM2 1PWM1 1PWM0 1BRM2 1BRM1 1BRM0 0000 0000 2PWM $0022 2PWM4 2PWM3 2PWM2 2PWM1 2PWM0 2BRM2 2BRM1 2BRM0 0000 ...

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    THIS PAGE LEFT BLANK INTENTIONALLY 3-6 MEMORY AND REGISTERS TPG MC68HC05BD3 ...

  • Page 33

    RESETS AND INTERRUPTS 4.1 RESETS The MC68HC05BD3 can be reset in four ways: by the initial power-on reset function active low input to the RESET pin opcode fetch from an illegal address, and by a COP ...

  • Page 34

    VDDR VDD VDD THRESHOLD (TYPICALLY 1-2V) 1 XTAL PIN 4 t oxov INTERNAL 2 CLOCK INTERNAL ADDRESS 2 BUS INTERNAL DATA 2 BUS RESET NOTES: 1. XTAL is not meant to represent frequency only used to represent ...

  • Page 35

    Note: COP time-out is prevented by periodically writing a “0” to bit 0 of address $3FF0. If the watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU. Because the internal reset signal is used, ...

  • Page 36

    UNSTACKING ORDER STACKING ORDER Register Flag Name – – – – – – SSCR – MSR MIF TOF MFTCSR RTIF – – – – 4-4 • • • 1 CONDITION CODE REGISTER 2 ACCUMULATOR ...

  • Page 37

    Maskable Hardware Interrupts If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are masked. Clearing the I-bit allows interrupt processing to occur. Note: The internal interrupt latch is cleared in the ...

  • Page 38

    IRQN bit 4 IRQ pin IRQ Wired ORed Interrupt signals IRQ 4-6 & (a) Interrupt Function Diagram t ILIH t ILIL t ILIL (b) Interrupt Mode Diagram Figure 4-3 External Interrupt Circuit and ...

  • Page 39

    Sync Signal Processor Interrupt The VSYNC interrupt is generated by the Sync Signal Processor (SSP) after a vertical sync pulse is detected as described in Section 8. The interrupt enable bit, VSIE, for the VSYNC interrupt is located at ...

  • Page 40

    Then CPU needs to check the SRW bit and set its MTX bit accordingly. Writing to the M-Bus Control register clears this bit. MAL - Arbitration Lost 1 (set) – Lost arbitration in master mode. 0 (clear) – No arbitration ...

  • Page 41

    MULTI-FUNCTION TIMER The MFT provides miscellaneous functions to the MC68HC05BD3 MCU. It includes a timer overflow function, real-time interrupt, and COP watchdog. The external interrupt (IRQ) triggering option is also set by this module’s MFT Control and Status Register. The ...

  • Page 42

    This bit is set when the 8-bit ripple counter overflows from $FF to $00; a timer overflow interrupt will occur, if TOFIE (bit 5) is set. TOF is cleared by writing a “0” to the bit. RTIF - Real Time ...

  • Page 43

    Table 5-1 COP Reset and RTI Rates RT1 RT0 Note: RT0 and RT1 should only be changed immediately after COP watchdog timer has been reset. MC68HC05BD3 Minimum COP reset period COP E ...

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    THIS PAGE LEFT BLANK INTENTIONALLY 5-4 MULTI-FUNCTION TIMER TPG MC68HC05BD3 ...

  • Page 45

    PULSE WIDTH MODULATION The MC68HC05BD3 has 16 PWM channels. Channel are dedicated PWM channels. Channel are shared with port C I/O pins, and are selected by the respective bits in Configuration register 1. PWM ...

  • Page 46

    The value of each PWM Data Register is continuously compared with the content of an internal counter to determine the state of each PWM channel output pin. Double buffering is not used in this PWM design. M=$00 T M=$01 M=$0F ...

  • Page 47

    M-BUS SERIAL INTERFACE M-Bus (Motorola Bus two-wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices fully compatible with the I bus minimizes the interconnection between devices and eliminates the need ...

  • Page 48

    Control register MEN MIEN MSTA MTX TXAK Interrupt SCL control SCL START, STOP detector and 7 SDA control SDA 7.2 M-Bus Protocol Normally, a standard communication is composed of four parts, 1) START signal, 2) slave address transmission, 3) data ...

  • Page 49

    MSB SCL SDA START signal MSB SCL SDA START signal Figure 7-2 M-Bus Transmission Signal Diagram 7.2.1 START Signal When the bus is free, i.e., no master device ...

  • Page 50

    Data Transfer Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in a direction specified by the R/W bit sent by the calling master. Each data byte is 8 bits long. Data can ...

  • Page 51

    Clock Synchronization Since wire-AND logic is performed on the SCL line, a high to low transition on SCL line will affect the devices connected to the bus. The devices start counting their low period and once a device's clock ...

  • Page 52

    M-Bus Address Register (MADR) Address bit 7 $0017 MAD7 MAD1-MAD7 are the slave address bits of the M-Bus module. 7.3.2 M-Bus Frequency Register (MFDR) Address bit 7 $0018 FD0-FD4 are used for clock rate selection. The serial bit clock ...

  • Page 53

    M-Bus Control Register (MCR) Address bit 7 bit 6 $0019 MEN MIEN Register bit definitions: MEN - M-Bus Enable 1 (set) – M-Bus interface system enabled. 0 (clear) – M-Bus interface system disabled. MIEN - M-Bus Interrupt Enable 1 ...

  • Page 54

    M-Bus Status Register (MSR) Address bit 7 $001A MCF The MIF and MAL bits are software clearable; while the other bits are read only. MCF - Data Transfer Complete 1 (set) – A byte transfer has been completed. 0 ...

  • Page 55

    SRW - Slave R/W Select 1 (set) – Read from slave, from calling master 0 (clear) – Write to slave from calling master. When MAAS is set, the R/W command bit of the calling address sent from the master is ...

  • Page 56

    TX TX/RX? Last byte Y transmitted RXAK= Write to MDR Generate STOP signal Figure 7-4 Flowchart of M-Bus Interrupt Routine 7-10 Clear MIF Y Master Mode Last byte to be read? Generate N STOP ...

  • Page 57

    Programming Considerations 7.4.1 Initialization Reset will put the M-Bus Control register to its default status. Before the interface can be used to transfer serial data, the following initialization procedure must be carried out. 1) Update Frequency Divider Register (MFDR) ...

  • Page 58

    MIF bit in the interrupt routine first. The MCF bit can be cleared by reading the M-Bus Data I/O Register (MDR) in receive mode or writing to the MDR in transmit mode. Software may serve the M-Bus I/O in the ...

  • Page 59

    LAMAR BSET 3,MCR BRA NXMAR ENMASR BCLR 5,MCR NXMAR LDA MDR STA RXBUF RTI 7.4.5 Generation of a Repeated START Signal At the end of data transfer, if the master still wants to communicate on the bus, it can generate ...

  • Page 60

    MAL=1 and MSTA=0. If one master attempts to start transmission while the bus is being controlled by another master, the transmission will be inhibited; the MSTA bit will be changed from without generating STOP ...

  • Page 61

    SYNC SIGNAL PROCESSOR The functions of the SSP include polarity correction, sync separation, sync pulse reshaper, sync pulse detectors, horizontal line counter, vertical frequency counter, and free running signals generator. In addition, interrupt can be generated for each vertical frame ...

  • Page 62

    POLARITY VSYNC CORRECTOR COMPOSITE POLARITY HSYNC CORRECTOR SYNC SEPARATOR & INSERTION SYNC SIGNAL $11 8 CONTROL REG. Figure 8-1 Sync Signal Processor Block Diagram 8.1.1.1 Separate Vertical Sync Input To test the polarity of the input sync signal, the duration ...

  • Page 63

    Positive polarity pure horizontal sync signal Negative polarity pure horizontal sync signal Figure 8-2 Sync Signal Polarity Correction 8.1.1.2 Separate Horizontal Or Composite Sync Input Since the input at HSYNC can be either a pure horizontal sync signal or a ...

  • Page 64

    Free-running Pseudo Sync Signal Generator If either HSYNC or VSYNC is absent, a free-running sync signal generator will be enabled. It generates a pseudo vertical sync at 63.5Hz (1/(tcyc x 31488)) and a pseudo horizontal sync at either 48.8KHz ...

  • Page 65

    Horizontal sync pulse counter is loaded into the Horizontal Sync Register before the Low Pulse Duration Counter is reset. Comparator compares the values of the Horizontal Sync Pulse Counter ...

  • Page 66

    System Clock VSYNC HSYNC Figure 8-4 Sync Signal Counters Block Diagram 8 PH2 VSYNIN Counter signal reset PH2 16 case1 PH2 16 case2 1. The value of the counter will be loaded into the register before it is reset. 2. ...

  • Page 67

    Registers There are seven registers associated with the Sync Signal Processor, these are described below. 8.3.1 Sync Signal Control & Status Register (SSCSR) Address bit 7 bit 6 $000C VPOL HPOL VPOL - Vertical Sync Input Polarity 1 (set) ...

  • Page 68

    SOUT - Sync Output Select 1 (set) – Use processed VSYNC and HSYNC inputs for VTTL and HTTL. 0 (clear) – Use internally generated sync signals for VTTL and HTTL. When cleared, the outputs to VTTL and HTTL are the ...

  • Page 69

    Vertical Frequency Registers (VFRS) Address bit 7 VFHR $000D VFLR $000E This 13-bit read only register pair contains information of the vertical frame frequency. An internal counter counts the number of internal clocks between two VSYNC pulses. The counted ...

  • Page 70

    The data can be read to determine if the line frequency is valid and to determine the video mode. However, the data is not valid if HDET or VDET bit is cleared or HOVER bit is set. User ...

  • Page 71

    System Operation The incoming signals can be either separate HSYNC and VSYNC or composite sync through HSYNC input. Polarity correction is performed before the sync signals go any further into the system. The sync pulse detection block continuously monitors ...

  • Page 72

    HOVER=1? N HSYNC too high 8 Set SOUT=1 Read registers Y VSIN=1? N Separated sync Set Normal mode Composite sync Set Normal mode 8-12 Clear 1st_time Init VSIN=0 Y VDET= HDET=1? N Set VSIN=1 B ...

  • Page 73

    CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05BD3. 9.1 Registers The MCU contains five registers, as shown in the programming model of Figure ...

  • Page 74

    Increasing memory address Unstack 9.1.2 Index register (X) The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area. ...

  • Page 75

    Interrupt (I) When this bit is set, all maskable interrupts are masked interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit ...

  • Page 76

    Register/memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump ...

  • Page 77

    Operation Description Condition codes Source Form Table 9-2 Register/memory instructions Function Load A from memory LDA A6 Load X from memory LDX AE Store A in memory STA Store X in memory STX Add memory to A ADD AB Add ...

  • Page 78

    Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear ...

  • Page 79

    Table 9-5 Read/modify/write instructions Function Increment INC Decrement DEC Clear CLR Complement COM Negate (two’s complement) NEG Rotate left through carry ROL Rotate right through carry ROR Logical shift left LSL Logical shift right LSR Arithmetic shift right ASR Test ...

  • Page 80

    Mnemonic INH ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS 9 BNE BPL BRA BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP Address mode abbreviations BSC ...

  • Page 81

    Table 9-7 Instruction set (Continued) Mnemonic INH IMM DIR COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA ...

  • Page 82

    Table 9-8 M68HC05 opcode map CPU CORE AND INSTRUCTION SET TPG MC68HC05BD3 ...

  • Page 83

    Addressing modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the ...

  • Page 84

    Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte ...

  • Page 85

    Relative The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are ...

  • Page 86

    THIS PAGE LEFT BLANK INTENTIONALLY 9 9-14 CPU CORE AND INSTRUCTION SET TPG MC68HC05BD3 ...

  • Page 87

    LOW POWER MODES The MC68HC05BD3 has only one low-power operating mode–the Wait Mode. The WAIT instruction provides the only mode that reduces the power required for the MCU by stopping CPU internal clock. The STOP instruction is not implemented in ...

  • Page 88

    COP Watchdog Timer Considerations The COP watchdog timer is always enabled in MC68HC05BD3. It will reset the MCU when it times out. For a system that must have intentional uses of the WAIT Mode, care must be taken to ...

  • Page 89

    ... OPERATING MODES The MC68HC05BD3/MC68HC05BD5/ MC68HC705BD3 MCU has two modes of operation, the User Mode and the Self-Check/ Bootstrap Mode. Figure 11-1 shows the flowchart of entry to these two modes, and Table 11-1 shows operating mode selection. RESET PB5 = V SELF-CHECK/ BOOTSTRAP MODE Figure 11-1 Flowchart of Mode Entering ...

  • Page 90

    ... Minimum hold time should be 2 clock cycles, after that it can be used as a normal IRQ function pin. 11.1 User Mode (Normal Operation) The normal operating mode of the MC68HC05BD3/MC68HC05BD5/ MC68HC705BD3 is the user mode. The user mode will be entered if the RESET line is brought low, and the IRQ pin is within its normal operational range (V enter the user mode. ...

  • Page 91

    RESET + 2 4K7 + Figure 11-3 MC68HC05BD3 Self-Test Circuit MC68HC05BD3 8 x 4K7 IRQ 10K PD0/SDA PC0/PWM8 PC1/PWM9 PD1/SCL PC2/PWM10 VSYNC PC3/PWM11 ...

  • Page 92

    ... Bootstrap Mode The bootstrap mode is provided in the EPROM part (MC68HC705BD3 mean of self-programming its EPROM with minimal circuitry entered on the rising edge of RESET if IRQ pin is at 1.8V and PB5 is at logic one. RESET must be held low for 4064 cycles after POR ...

  • Page 93

    ELECTRICAL SPECIFICATIONS This section contains the electrical specifications for MC68HC05BD3. 12.1 Maximum Ratings (Voltages referenced RATINGS Supply Voltage Input Voltage IRQ Current Drain per pin excluding V DD Operating Temperature Storage Temperature Range This device contains ...

  • Page 94

    DC Electrical Characteristics Table 12-1 DC Electrical Characteristics for MC68HC05BD3 (V =5.0Vdc 10 CHARACTERISTICS Output voltage I = –10 A LOAD I = +10 A LOAD Output high voltage (I PA0-PA7, PB0-PB1, PC6-PC7, PD0-PD1 Output low voltage ...

  • Page 95

    Control Timing (V =5.0Vdc 10%, V =0Vdc, temperature range CHARACTERISTICS Frequency of operation Crystal option External clock option Internal operating frequency (f Crystal External clock Processor cycle time Crystal oscillator start-up time External RESET ...

  • Page 96

    M-Bus Timing (V =5.0Vdc 10 START condition hold time Clock low period Clock high period Data set-up time Data hold time START condition set-up time (for repeated START condition only) STOP condition set-up time (V =5.0Vdc 10%, ...

  • Page 97

    Sync Signal Processor Timing Table 12-5 Sync Signal Processor Timing (V =5.0Vdc 10%, V =0Vdc, temperature range PARAMETER VSYNC input sync pulse HSYNC input sync pulse (except for composite sync input) VTTL output sync ...

  • Page 98

    THIS PAGE LEFT BLANK INTENTIONALLY 12 12-6 ELECTRICAL SPECIFICATIONS TPG MC68HC05BD3 ...

  • Page 99

    MECHANICAL SPECIFICATIONS This section provides the mechanical dimension for the 42-pin SDIP and 40-pin DIP packages for the MC68HC05BD3. 13.1 42-Pin SDIP Package (Case 858-01 13.2 40-Pin DIP Package (Case 711-03) ...

  • Page 100

    THIS PAGE LEFT BLANK INTENTIONALLY 13 13-2 MECHANICAL SPECIFICATIONS TPG MC68HC05BD3 ...

  • Page 101

    ... MC68HC705BD3 The MC68HC705BD3 is functionally equivalent to MC68HC05BD3, but with increased RAM size to 256 bytes and the user ROM is replaced by an 7.75K-bytes user EPROM (located from $2000 to $3EFF). The entire MC68HC05BD3 data sheet applies to the MC68HC705BD3, with exceptions outlined in the section. 14.1 Features • ...

  • Page 102

    ... HSYNC Period Width Register User EPROM 7936 Bytes $3EFF $3F00 Unused $3FDF $3FE0 Bootstrap Vectors 16 Bytes $3FEF $3FF0 User Vectors 16 Bytes $3FFF $3FF0 $3FF2 $3FF4 $3FF6 $3FF8 $3FFA $3FFC $3FFE MC68HC705BD3 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 Unused $12 Unused $13 Unused ...

  • Page 103

    ... Programming power switched off to EPROM array. 14.3.2 EPROM Programming Sequence Programming the EPROM of the MC68HC705BD3 is as follows: 1) Set the ELAT bit. 2) Write the data to be programmed to the address to be programmed. 3) Set the PGM bit. 4) Delay for the appropriate amount of time. ...

  • Page 104

    ... BSET 0,PCR JSR DELAY CLR PCR 14.4 DC Electrical Characteristics Table 14-2 DC Electrical Characteristics for MC68HC705BD3 (V =5.0Vdc 10 CHARACTERISTICS Output voltage I = –10 A LOAD I = +10 A LOAD Output high voltage (I PA0-PA7, PB0-PB1, PC6-PC7, PD0-PD1 Output low voltage (I LOAD PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, PWM0-PWM7 Input high voltage ...

  • Page 105

    MC68HC05BD5 The MC68HC05BD5 is functionally equivalent to MC68HC05BD3, but with increased RAM size of 256 bytes and ROM size of 7.75K-bytes. The entire MC68HC05BD3 data sheet applies to the MC68HC05BD5, with exceptions outlined in the section. 15.1 Features • Functionally ...

  • Page 106

    MC68HC05BD5 $0000 Port A Data Register I/O Port B Data Register 48 Bytes $002F Port C Data Register $0030 Port D Data Register Unused Port A Data Direction Register Port B Data Direction Register $007F $0080 Port C ...

  • Page 107

    DC Electrical Characteristics Table 15-1 DC Electrical Characteristics for MC68HC05BD5 (V =5.0Vdc 10%, V =0Vdc, temperature range CHARACTERISTICS Output voltage I = –10 A LOAD I = +10 A LOAD Output high voltage (I ...

  • Page 108

    THIS PAGE LEFT BLANK INTENTIONALLY 15 15-4 MC68HC05BD5 TPG MC68HC05BD3 ...

  • Page 109

    ... PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3 MC68HC05BD5 TPG ...

  • Page 110

    ... GENERAL DESCRIPTION 2 PIN DESCRIPTION AND I/O PORTS 3 MEMORY AND REGISTERS 4 RESETS AND INTERRUPTS 5 MULTI-FUNCTION TIMER 6 PULSE WIDTH MODULATION 7 M-BUS SERIAL INTERFACE 8 SYNC SIGNAL PROCESSOR 9 CPU CORE AND INSTRUCTION SET 10 LOW POWER MODES 11 OPERATING MODES 12 ELECTRICAL SPECIFICATIONS 13 MECHANICAL SPECIFICATIONS 14 MC68HC705BD3 15 MC68HC05BD5 TPG ...

  • Page 111

    Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...

  • Page 112

    MC68HC05BD3D/H ...