MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 70

• Manufacturer Part Number: MC68HC705BD3
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8
sync input. The data can be read to determine if the line frequency is valid and to determine the
video mode. However, the data is not valid if HDET or VDET bit is cleared or HOVER bit is set.
User has to determine whether the incoming signal is separate sync or composite sync. If
composite sync signal is input, the actual number of horizontal lines is the value in LFR plus one;
because the internal line counter that counts the horizontal sync pulses is rising-edge triggering.
If the incoming signal is a composite signal, one horizontal line counting is missed.
8.3.4
This is a read/write register. Interrupt will be generated at the leading edge of VSYNC if the VSIE
bit is set, I bit in CCR is cleared. The VSYNC interrupt vectors are at $3FF8 and $3FF9, and the
interrupt latch is cleared after the interrupt vectors have been fetched.
VSIE - Vsync Interrupt Enable
This bit enables and disables the Vsync interrupt.
8.3.5
This 8-bit read only register contains the period of incoming horizontal sync signal. It is sampled
by t
horizontal sync signal is asynchronous to the system clock, the SSP is designed so that the
maximum counting error of HPWR is –2. User should use the LFR to calculate the HSYNC
frequency if very accurate frequency detection is needed. If HPWR overflows, the HDET in
SSCSR will be cleared. Therefore the minimum valid HSYNC is 256t
equals to 2MHz.
Note:
8-10
CYC
1 (set)
0 (clear) –
Address
Address
so the horizontal period is equal to HPWR x 0.5 s if t
$0011
$001E
It is not guaranteed that the HPWR counting is correct for the first HSYNC period after
the trailing edge of VSYNC.
Sync Signal Control Register (SSCR)
Horizontal Sync Period Width Register (HPWR)
HPWR7 HPWR6 HPWR5 HPWR4 HPWR3 HPWR2 HPWR1 HPWR0
VSIE
–
bit 7
bit 7
Vsync interrupt enabled.
Vsync interrupt disabled.
bit 6
bit 6
SYNC SIGNAL PROCESSOR
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
CYC
bit 1
bit 1
is at 2MHz. As the incoming
CYC
bit 0
bit 0
, i.e. 7.8125KHz if t
0000 0000
0000 0000
on reset
on reset
MC68HC05BD3
State
State
CYC
TPG