MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 15

• Manufacturer Part Number: MC68HC705BD3
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Figure
Number
MC68HC05BD3
1-1
2-1
2-2
2-3
3-1
4-1
4-2
4-3
6-1
7-1
7-2
7-3
7-4
8-1
8-2
8-3
8-4
8-5
8-6
9-1
9-2
10-1
11-1
11-2
11-3
12-1
14-1
15-1
MC68HC05BD3/MC68HC705BD3/MC68HC05BD5 Block Diagram ......................1-2
Pin Assignment for 40-pin DIP Package.................................................................2-2
Pin Assignment for 42-pin SDIP Package ..............................................................2-3
Parallel Port I/O Circuitry ........................................................................................2-6
Memory Map ..........................................................................................................3-3
Power-On Reset and RESET Timing......................................................................4-2
Interrupt Stacking Order .........................................................................................4-4
External Interrupt Circuit and Timing ......................................................................4-6
8-Bit PWM Output Waveforms................................................................................6-2
M-Bus Interface Block Diagram ..............................................................................7-2
M-Bus Transmission Signal Diagram ......................................................................7-3
Clock Synchronization ............................................................................................7-5
Flowchart of M-Bus Interrupt Routine.....................................................................7-10
Sync Signal Processor Block Diagram ...................................................................8-2
Sync Signal Polarity Correction ..............................................................................8-3
Sync Separator.......................................................................................................8-4
Sync Signal Counters Block Diagram.....................................................................8-6
Vertical Frequency Counter Timing ........................................................................8-6
Typical Monitor System Operation..........................................................................8-12
Programming model ...............................................................................................9-1
Stacking order ........................................................................................................9-2
WAIT Flowchart ....................................................................................................10-2
Flowchart of Mode Entering .................................................................................11-1
Self-Check Mode Timing ......................................................................................11-2
MC68HC05BD3 Self-Test Circuit..........................................................................11-3
M-Bus Timing........................................................................................................12-4
MC68HC705BD3 Memory Map............................................................................14-2
MC68HC05BD5 Memory Map..............................................................................15-2
LIST OF FIGURES
TITLE
Number
Page
TPG
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