MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 22

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MC68HC705BD3

Manufacturer Part Number
MC68HC705BD3
Description
High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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2
2.2
2-2
PC6/PWM14/VTTL,
PC7/PWM15/HTTL
PD0/SDA,
PD1/SCL
PWM0 to PWM7
HSYNC, VSYNC
PIN NAME
Pin Assignments
40-pin DIP
3-1, 38-34
PIN No.
32, 33
24, 25
39, 40
Figure 2-1 Pin Assignment for 40-pin DIP Package
PIN DESCRIPTION AND I/O PORTS
IRQ/ VPP
RESET
3-1, 40-38, 36,
EXTAL
PWM2
PWM1
PWM0
42-pin SDIP
XTAL
VDD
VSS
PB5
PB4
PB3
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
PIN No.
33, 34
25, 26
41, 42
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
These two port C I/O lines are shared with the PWM and Sync Signal
Processor. Configuration for use are set by the Configuration
register 1 ($0A) and Configuration register 2 ($0B).
These two port D I/O lines are shared with the M-Bus lines SDA and
SCL. When configured as M-Bus lines in Configuration
register 2 ($0B), these pins become +5V open-drain pins.
These eight pins are dedicated for the 8-bit PWM channel 0 to 7.
These two pins are for video sync signals input from the host
computer. The polarity of the input signals can either be positive or
negative. These two pins contain internal Schmitt triggers as part of
their inputs to improve noise immunity
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSYNC
HSYNC
PWM3
PWM4
PWM5
PWM6
PWM7
PC7/PWM15/HTTL
PC6/PWM14/VTTL
PC5/PWM13
PC4/PWM12
PC3/PWM11
PC2/PWM10
PC1/PWM9
PC0/PWM8
PD1/SCL
PD0/SDA
PA0
PA1
PA2
DESCRIPTION
MC68HC05BD3
TPG

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