MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 67

• Manufacturer Part Number: MC68HC705BD3
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.3
There are seven registers associated with the Sync Signal Processor, these are described below.
8.3.1
VPOL - Vertical Sync Input Polarity
Vertical Sync Input Polarity flag indicates the polarity of the incoming signal at the VSYNC input.
HPOL - Horizontal Sync Input Polarity
Horizontal Sync Input Polarity flag indicates the polarity of the incoming signal at the HSYNC
input.
VDET - Vertical Sync Signal Detect
Vertical Sync Signal Detect flag, if set, indicates an active input vertical sync signal has been
detected. If cleared, it indicates there is no active signal, and the VTTL will output the internally
generated Vsync signal. An active vertical sync signal is defined as:
VDET = (VSYNC pulse width < 480 s or 960t
HDET - Horizontal Sync Signal Detect
Horizontal Sync Signal Detect flag, if set, indicates an active input horizontal sync signal has been
detected. If cleared, it indicates there is no active signal, and the HTTL will output the internally
generated Hsync signal. An active horizontal sync signal is defined as:
HDET=(HSYNC pulse width < 8 s or 16t
MC68HC05BD3
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Address
$000C
Registers
Sync Signal Control & Status Register (SSCSR)
VPOL
–
–
–
–
bit 7
VSYNC input is positive polarity.
VSYNC input is negative polarity.
HSYNC input is positive polarity.
HSYNC input is negative polarity.
An active vertical sync is detected at VSYNC input.
No vertical sync signal at VSYNC input; use internal generated
Vsync for VTTL.
An active horizontal sync is detected at HSYNC input.
No horizontal sync signal at HSYNC input; use internal generated
Hsync for HTTL.
HPOL
bit 6
VDET
SYNC SIGNAL PROCESSOR
bit 5
CYC
)·(9 s or 18t
HDET
CYC
bit 4
)·(VSYNC period < 65.5ms or 131x10
SOUT
bit 3
CYC
< HSYNC period < 128 s or 256t
INSRTB
bit 2
FOUT
bit 1
VSIN
bit 0
3
t
CYC
0000 0000
on reset
State
)
CYC
)
TPG
8-7
8