MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 11

• Manufacturer Part Number: MC68HC705BD3
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Paragraph
Number
MC68HC05BD3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
8.1
8.1.1
8.1.1.1
8.1.1.2
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
Programming Considerations ................................................................................7-11
Functional Blocks...................................................................................................8-1
VSYNC Interrupt....................................................................................................8-5
Registers ...............................................................................................................8-7
System Operation ..................................................................................................8-11
Registers ...............................................................................................................9-1
M-Bus Address Register (MADR) ....................................................................7-6
M-Bus Frequency Register (MFDR).................................................................7-6
M-Bus Control Register (MCR) ........................................................................7-7
M-Bus Status Register (MSR)..........................................................................7-8
M-Bus Data I/O Register (MDR) ......................................................................7-9
Initialization ......................................................................................................7-11
Generation of a START Signal and the First Byte of Data Transfer..................7-11
Software Responses after Transmission or Reception of a Byte .....................7-11
Generation of the STOP Signal........................................................................7-12
Generation of a Repeated START Signal ........................................................7-13
Slave Mode ......................................................................................................7-13
Arbitration Lost .................................................................................................7-13
Polarity Correction............................................................................................8-1
Sync Detection.................................................................................................8-3
Free-running Pseudo Sync Signal Generator ..................................................8-4
Sync Separation...............................................................................................8-4
Vertical Sync Pulse Reshaper..........................................................................8-5
Sync Signal Counters ......................................................................................8-5
Sync Signal Control & Status Register (SSCSR).............................................8-7
Vertical Frequency Registers (VFRS) ..............................................................8-9
Line Frequency Registers (LFRs) ....................................................................8-9
Sync Signal Control Register (SSCR)..............................................................8-10
Horizontal Sync Period Width Register (HPWR)..............................................8-10
Accumulator (A) ...............................................................................................9-1
Index register (X)..............................................................................................9-2
Program counter (PC) ......................................................................................9-2
Stack pointer (SP) ............................................................................................9-2
Condition code register (CCR).........................................................................9-2
Separate Vertical Sync Input ......................................................................8-2
Separate Horizontal Or Composite Sync Input ..........................................8-3
CPU CORE AND INSTRUCTION SET
SYNC SIGNAL PROCESSOR
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