NAND04GW3B2AN1F NUMONYX [Numonyx B.V], NAND04GW3B2AN1F Datasheet
NAND04GW3B2AN1F
Related parts for NAND04GW3B2AN1F
NAND04GW3B2AN1F Summary of contents
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... Features ■ High density NAND Flash Memory – Gbit memory array – 256 Mbit spare area – Cost effective solution for mass storage applications ■ NAND Interface – x8 bus width – Multiplexed Address/ Data ■ Supply voltage – 3.0V device ...
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... Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Inputs/Outputs (I/O0-I/O7 3.2 Address Latch Enable (AL 3.3 Command Latch Enable (CL 3.4 Chip Enable ( 3.5 Read Enable ( 3.6 Power-Up Read Enable, Lock/Unlock Enable (PRL 3.7 Write Enable ( 3.8 Write Protect (WP 3.9 Ready/Busy (RB ...
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... Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1 Blocks Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2 Blocks Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3 Blocks Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4 Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.1 Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2 NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.3 Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.5 Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.6.1 8.6.2 9 Program and Erase times and endurance cycles . . . . . . . . . . . . . . . . . 40 Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Random Data Input in page ...
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Contents 10 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND04GW3B2B, NAND08GW3B2A List of tables Table 1. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... List of figures List of figures Figure 1. Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Logic Diagram Figure 3. TSOP48 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Read Operations Figure 6. Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. Random Data Input During Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10 ...
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... During Cache Programming, the device loads the data in a Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array. During Cache Reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O Buffers to be read. The device has the Chip Enable Don’ ...
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... Description For information on how to order these options refer to Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to ’1’. See Table 1: Product Table 1. Product Description Bus Part Number Density Width NAND04GW3B2B ...
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NAND04GW3B2B, NAND08GW3B2A Figure 2. Logic Diagram Table 2. Signal Names I/O0 PRL NAND FLASH PRL V SS Data ...
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Description Figure 3. TSOP48 Connections 10/58 NAND04GW3B2B, NAND08GW3B2A NAND FLASH ...
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... Memory array organization The memory array is made up of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 64 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store Error correction Codes, software flags or Bad Block identification ...
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... Memory array organization Figure 4. Memory Array Organization Block Page 12/58 x8 bus width Block = 64 Pages Page = 2112 Bytes (2,048 + 64) Main Area 8 bits 2048 Bytes 64 Bytes Page Buffer, 2112 Bytes 64 2,048 Bytes 8 bits Bytes NAND04GW3B2B, NAND08GW3B2A AI12468 ...
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... Interface. When CL is high, the inputs are latched on the rising edge of Write Enable. 3.4 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, V high while the device is busy, the device remains selected and does not go into standby IH mode ...
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... V Supply Voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V Table 19) to protect the device from any involuntary program/erase during power-transitions. ...
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... Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the lock status, the Electronic Signature and the Unique Identifier. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low ...
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... Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. ...
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NAND04GW3B2B, NAND08GW3B2A 5 Command set All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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... Device operations The following section gives the details of the device operations. 6.1 Read Memory Array At Power-Up the device defaults to Read mode. To enter Read mode from another mode the Read command must be issued, see issued, subsequent consecutive Read commands only require the confirm command code (30h) ...
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NAND04GW3B2B, NAND08GW3B2A Figure 5. Read Operations I/O Address Input 00h Command Code tBLBH1 30h Data Output (sequentially) Command Busy Code Device operations ai12469 19/58 ...
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Device operations Figure 6. Random Data Output During Sequential Data Output tBLBH1 (Read Busy time Address 30h I/O 00h Inputs Cmd Cmd Code Code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main Area 20/58 Busy 05h ...
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NAND04GW3B2B, NAND08GW3B2A 6.2 Cache Read The Cache Read operation is used to improve the read throughput by reading data using the Cache Register. As soon as the user starts to read one page, the device automatically loads the next page ...
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... Device operations 6.3 Page Program The Page Program operation is the standard operation to program data to the memory array. Generally, the page is programmed sequentially, however the device does support Random Input within a page recommended to address pages sequentially within a given block. The memory array is programmed by page, however partial page programming is allowed where any number of Bytes (1 to 2112) can be programmed ...
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NAND04GW3B2B, NAND08GW3B2A Figure 8. Page Program Operation RB I/O 80h Page Program Setup Code Figure 9. Random Data Input During Sequential Data Input RB Address I/O 80h Data Intput Inputs Cmd Code 5 Add cycles Row Add 1,2,3 Col Add ...
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... The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block ...
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NAND04GW3B2B, NAND08GW3B2A Figure 11. Page Copy Back Program with Random Data Input Source I/O 35h 00h Add Inputs Read Code tBLBH1 (Read Busy time) RB Target 85h Data Add Inputs Copy Back Code Unlimited number of repetitions Busy Device operations ...
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... Cache Register. The Cache Program operation can only be used within one block. The Cache Register allows new data to be input while the previous data that was transferred to the Page Buffer is programmed into the memory array. The following sequence is required to perform a Cache Program operation (refer to 1 ...
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... The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued during any operation, the operation will be aborted was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. ...
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Device operations 6.8 Read Status Register The device contains a Status Register which provides information on the current or previous Program or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status ...
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... The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to ‘0’ the operation has completed successfully. The Error Bit SR0 Cache Program operation, indicates a failure on Page N. ...
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Device operations 6.9 Read Electronic Signature The device contains a Manufacturer Code and Device Code. To read these codes three steps are required: 1. One Bus Write cycle to issue the Read Electronic Signature command (90h) 2. One Bus Write ...
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NAND04GW3B2B, NAND08GW3B2A Table 12. Electronic Signature Byte 4 I/O I/O1-I/O0 I/O2 I/O7, I/O3 I/O5-I/O4 I/O6 Definition Page Size (Without Spare Area) Spare Area Size (Byte / 512 Byte) Minimum sequential access time Block Size (without Spare Area) Organization Device operations ...
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... It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations recommended to keep down. In addition, to protect the memory from any involuntary program/erase operations during power-transitions, the device has an internal voltage detector which disables all functions whenever V ...
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NAND04GW3B2B, NAND08GW3B2A If the Start Block Address is the same as the End Block Address, only one block is unlocked. Only one consecutive area of blocks can be unlocked at any one time not possible to unlock multiple ...
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Data Protection Figure 15. Read Block Lock Status Operation W R I/O 7Ah Read Block Lock Status Command Table 13. Block Lock Status Status I/O7-I/O3 Locked Unlocked Locked-Down Unlocked in Locked- Down Area Don’t Care. 34/58 tWHRL ...
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NAND04GW3B2B, NAND08GW3B2A Figure 16. Block Protection State Diagram Block Unlock Command (start + end block address) Unlocked in Locked Area Blocks Lock-Down Command 1. PRL must be High for the software commands to be accepted. Power-Up Locked Blocks Lock-Down Blocks ...
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... Error Correction Code, to extend the number of program and erase cycles and increase the data retention. To help integrate a NAND memory into an application Numonyx can provide a File System OS Native reference software, which supports the basic commands of file management. Contact the nearest Numonyx sales office for more details. ...
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NAND04GW3B2B, NAND08GW3B2A Table 14. Block failure Operation Erase Program Read Figure 17. Bad Block management flowchart Procedure Block Replacement Block Replacement or ECC START Block Address = Block 0 Increment Block Address Data Update NO Bad Block table = FFh? ...
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... After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a Garbage Collection algorithm Garbage Collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 18: Garbage Figure 18 ...
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NAND04GW3B2B, NAND08GW3B2A An ECC model is available in VHDL or Verilog. Contact the nearest Numonyx sales office for more details. Figure 19. Error Detection 8.6 Hardware simulation models 8.6.1 Behavioral simulation models Denali Software Corporation models are platform independent functional ...
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Program and Erase times and endurance cycles 9 Program and Erase times and endurance cycles The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 15. Table 15. Program, Erase Times and ...
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NAND04GW3B2B, NAND08GW3B2A 10 Maximum rating Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...
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DC and AC parameters 11 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from ...
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NAND04GW3B2B, NAND08GW3B2A Figure 20. Equivalent Testing Circuit for AC Characteristics Measurement Table 19. DC Characteristics Symbol Parameter I DD1 Operating I Current DD2 I DD3 Standby current (TTL) I DD4 I Standby Current (CMOS) DD5 I Input Leakage Current LI ...
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DC and AC parameters Table 20. AC Characteristics for Command, Address, Data Input Alt. Symbol Symbol t Address Latch Low to Write Enable high ALLWH t ALS t Address Latch High to Write Enable high ALHWH t Command Latch High ...
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NAND04GW3B2B, NAND08GW3B2A Table 21. AC Characteristics for operations t t Command Latch Low to Read Enable Low CLLRL CLR t t Data Hi-Z to Read Enable Low DZRL Chip Enable High to Output Hi-Z EHQZ CHZ t ...
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DC and AC parameters Figure 22. Address Latch AC Waveforms CL tELWH (E Setup time) E tWLWH W tWHWL tALHWH (AL Setup time) tWHALL (AL Hold time) AL tDVWH (Data Setup time) Adrress I/O cycle 1 46/58 tCLLWH (CL Setup ...
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NAND04GW3B2B, NAND08GW3B2A Figure 23. Data Input Latch AC Waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O 1. Data In Last is 2112. Figure 24. Sequential Data Output after Read AC waveforms E R tRLQV (R ...
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DC and AC parameters Figure 25. Read Status Register AC Waveform CL tCLHWH E tELWH W R (Data Setup time) I/O Figure 26. Read Electronic Signature AC Waveform I/O 90h Read Electronic Signature Command 1. ...
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NAND04GW3B2B, NAND08GW3B2A Figure 27. Page Read operation AC Waveform CL E tWLWL Add.N Add.N Add.N I/O 00h cycle 1 cycle 2 cycle 3 Command Address N Input Code tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N ...
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DC and AC parameters Figure 28. Page Program AC waveform CL E tWLWL (Write Cycle time Add.N Add.N I/O 80h cycle 1 cycle 2 RB Page Program Setup Code 50/58 tWLWL tWHWH Add.N Add.N Add.N N cycle ...
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NAND04GW3B2B, NAND08GW3B2A Figure 29. Block Erase AC Waveform CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command Figure 30. Reset AC Waveform I/O ...
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DC and AC parameters Figure 31. Program/Erase Enable Waveform W tVHWH WP RB I/O Figure 32. Program/Erase Disable Waveform W tVLWH WP High RB I/O 52/58 80h 80h NAND04GW3B2B, NAND08GW3B2A 10h 10h ai12477 ai12478 ...
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NAND04GW3B2B, NAND08GW3B2A 11.1 Ready/Busy Signal Electrical Characteristics Figure 34, Figure 33 signal. The value required for the resistor R So, where I is the sum of the input currents of all the devices tied to the Ready/Busy signal ...
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DC and AC parameters Figure 35. Resistor Value Versus Waveform Timings For Ready/Busy Signal 25°C. 11.2 Data Protection The Numonyx NAND device is designed to guarantee Data Protection during Power Transitions detection circuit disables all ...
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NAND04GW3B2B, NAND08GW3B2A 12 Package mechanical Figure 37. TSOP48 - 48 lead Plastic Thin Small Outline mm, Package Outline DIE 1. Drawing is not to scale. Table 22. TSOP48 - 48 lead Plastic Thin Small ...
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... E = Lead Free Package, Standard Packing F = Lead Free Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest Numonyx Sales Office. ...
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... RHBL Waveform. Data integrity of 100,000 specified for ECC implemented. Note 2 removed below Note 1 added below t changed into t WHBH2 Note 3 added below Section 8.2: NAND Flash memory failure modes Software algorithms. t added in Table 20: AC Characteristics for Command, WHALL 3 Address, Data Input. t Characteristics for operations ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE ...