NAND04GW3B2AN1F NUMONYX [Numonyx B.V], NAND04GW3B2AN1F Datasheet - Page 24

• Manufacturer Part Number: NAND04GW3B2AN1F
• Description: 4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
• Manufacturer: NUMONYX [Numonyx B.V]

Device operations
6.4
Table 8.
Figure 10. Copy Back Program
1. Copy back program is only permitted between odd address pages or even address pages.
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RB
I/O
Read
Code
00h
Copy Back Program
The Copy Back Program operation is used to copy the data stored in one page and
reprogram it in another page.
The Copy Back Program operation does not require external memory and so the operation
is faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
If the Copy Back Program operation fails an error is signalled in the Status Register.
However as the standard external ECC cannot be used with the Copy Back Program
operation bit error due to charge loss cannot be detected. For this reason it is recommended
to limit the number of Copy Back Program operations on the same data and or to improve
the performance of the ECC.
The Copy Back Program operation requires four steps:
1.
2.
3.
To see the Data Input cycle for modifying the source page and an example of the Copy Back
Program operation refer to
A data input cycle to modify a portion or a multiple distant portion of the source page, is
shown in
Copy Back Program addresses
The first step reads the source page. The operation copies all 2112 Bytes from the
page into the Data Buffer. It requires:
–
–
–
When the device returns to the ready state (Ready/Busy High), the next bus write cycle
of the command is given with the 5 bus cycles to input the target page address. See
Table 8
Then the confirm command is issued to start the P/E/R Controller.
Add Inputs
Source
Figure 11: Page Copy Back Program with Random Data
Density
One bus write cycle to setup the command
5 bus write cycles to input the source page address
One bus write cycle to issue the confirm command code
4 Gbits
8 Gbits
for the addresses that must be the same for the source and target page.
(Read Busy time)
tBLBH1
35h
Busy
Figure 10: Copy Back
Copy Back
Code
85h
Add Inputs
Target
Source and target page addresses
Program.
NAND04GW3B2B, NAND08GW3B2A
(Program Busy time)
no constraint
tBLBH2
same A30
10h
Input.
Busy
Read Status Register
70h
SR0
ai09858b