NAND04GW3B2AN1F NUMONYX [Numonyx B.V], NAND04GW3B2AN1F Datasheet - Page 14

• Manufacturer Part Number: NAND04GW3B2AN1F
• Description: 4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
• Manufacturer: NUMONYX [Numonyx B.V]

Signal descriptions
3.7
3.8
3.9
3.10
3.11
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Write Enable (W)
The Write Enable input, W, controls writing to the Command Interface, Input Address and
Data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10µs (min) is required before the
Command Interface is ready to accept a command. It is recommended to keep Write Enable
high during the recovery time.
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, V
program or erase operations.
It is recommended to keep the Write Protect pin Low, V
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
Controller is currently active.
When Ready/Busy is Low, V
operation completes Ready/Busy goes High, V
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
Refer to the
calculate the value of the pull-up resistor.
V
V
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V
Table
Each device in a system should have V
widths should be sufficient to carry the required program and erase currents
V
Ground, V
ground.
DD
DD
SS
provides the power supply to the internal core of the memory device. It is the main
19) to protect the device from any involuntary program/erase during power-transitions.
Ground
Supply Voltage
SS,
Section 11.1: Ready/Busy Signal Electrical Characteristics
is the reference for the power supply. It must be connected to the system
OL
, a read, program or erase operation is in progress. When the
DD
decoupled with a 0.1µF capacitor. The PCB track
OH
.
IL
, the device does not accept any
NAND04GW3B2B, NAND08GW3B2A
IL
, during power-up and power-down.
DD
is below V
for details on how to
LKO
(see