NAND04GW3B2AN1F NUMONYX [Numonyx B.V], NAND04GW3B2AN1F Datasheet - Page 21

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NAND04GW3B2AN1F

Manufacturer Part Number
NAND04GW3B2AN1F
Description
4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
NAND04GW3B2B, NAND08GW3B2A
6.2
Figure 7.
1. For NAND08GW3B2A, A30 can not be changed during the Cache Read Operation.
RB
R
I/O
Setup
Read
Code
Cache Read
The Cache Read operation is used to improve the read throughput by reading data using
the Cache Register. As soon as the user starts to read one page, the device automatically
loads the next page into the Cache Register.
An Cache Read operation consists of three steps (see
1.
2.
3.
The Start Address must be at the beginning of a page (Column Address = 00h, see
Address
(t
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the Cache Read operation has started, the Status Register can be read using the
Read Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the Cache Register
is ready to download new data.
To exit the Cache Read operation an Exit Cache Read command must be issued (see
Table 7:
If the Exit Cache Read command is issued while the device is internally reading page n+1,
page n will still be output, but not page n+1.
Cache Read Operation
00h
BLBH1
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command).
Five (refer to
Address.
One bus cycle is required to issue the Cache Read confirm command to start the P/E/R
Controller.
), see
Address
Inputs
Commands).
Definition). This allows the data to be output uninterrupted after the latency time
Figure 7: Cache Read
(Read Busy time)
tBLBH1
Confirm
Cache
Read
Code
Table 5: Address
31h
Busy
tRHRL2
1st page
Insertion) bus cycles are then required to input the Start
Operation.
2nd page
Block N
3rd page
tRHRL2
Data Output
Table 7:
last page (1)
Commands):
Cache
Device operations
Read
Code
Exit
34h
tBLBH4
ai8661c
Table 6:
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