NAND04GW3B2AN1F NUMONYX [Numonyx B.V], NAND04GW3B2AN1F Datasheet - Page 22

• Manufacturer Part Number: NAND04GW3B2AN1F
• Description: 4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
• Manufacturer: NUMONYX [Numonyx B.V]

Device operations
6.3
6.3.1
6.3.2
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Page Program
The Page Program operation is the standard operation to program data to the memory
array. Generally, the page is programmed sequentially, however the device does support
Random Input within a page.
It is recommended to address pages sequentially within a given block.
The memory array is programmed by page, however partial page programming is allowed
where any number of Bytes (1 to 2112) can be programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is four. After exceeding this a Block Erase command must be issued before any further
program operations can take place in that page.
Sequential Input
To input data sequentially the addresses must be sequential and remain in one block.
For Sequential Input each Page Program operation consists of five steps (see
Page Program
1.
2.
3.
4.
5.
Random Data Input in page
During a Sequential Input operation, the next sequential address to be programmed can be
replaced by a random address, by issuing a Random Data Input command. The following
two steps are required to issue the command:
1.
2.
Random Data Input can be repeated as often as required in any given page.
Once the program operation has started the Status Register can be read using the Read
Status Register command. During program operations the Status Register will only flag
errors for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands will be
accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in Read Status Register mode until another valid command is written to
the Command Interface.
One bus cycle is required to setup the Page Program (Sequential Input) command (see
Table 7:
Five bus cycles are then required to input the program address (refer to
Address
The data is then loaded into the Data Registers.
One bus cycle is required to issue the Page Program confirm command to start the
P/E/R Controller. The P/E/R will only start if the data has been loaded in step 3.
the P/E/R Controller then programs the data into the array.
One bus cycle is required to setup the Random Data Input command (see
Commands)
Two bus cycles are then required to input the new column address (refer to
Address
Commands).
Insertion).
Insertion)
Operation):
NAND04GW3B2B, NAND08GW3B2A
Table 5:
Figure 8:
Table 7:
Table 5: