NAND04GW3B2AN1F NUMONYX [Numonyx B.V], NAND04GW3B2AN1F Datasheet - Page 16

• Manufacturer Part Number: NAND04GW3B2AN1F
• Description: 4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
• Manufacturer: NUMONYX [Numonyx B.V]

Bus operations
4.5
4.6
16/58
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 4.
1. WP must be V
Table 5.
1. Any additional address input cycles will be ignored.
2. A30 is only valid for the NAND08GW3B2A.
Table 6.
Cycle
Command set
Bus
Command Input
2
Bus Operation
1
3
4
5
Address Input
Write Protect
nd
rd
th
th
st
Data Output
Data Input
(1)
Standby
A12 - A17
A18 - A29
A18 - A30
Address
A0 - A11
Bus Operations
Address Insertion
Address Definition
I/O7
A19
A27
V
V
A7
IH
IL
IL
when issuing a program or erase command.
I/O6
A18
A26
V
A6
V
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
IL
IL
V
AL
V
V
V
X
X
I/O5
IH
A17
A25
IL
IL
IL
V
V
A5
IL
IL
V
CL
V
V
V
X
X
IH
IL
IL
IL
I/O4
A16
A24
V
V
A4
Block Address (NAND04GW3B2B)
Block Address (NAND08GW3B2A)
IL
IL
Falling
V
V
V
R
X
X
IH
IH
IH
NAND04GW3B2B, NAND08GW3B2A
Column Address
I/O3
A11
A15
A23
V
A3
Page Address
IL
Rising
Rising
Rising
Definition
V
W
X
X
IH
A30
I/O2
A10
A14
A22
A2
V
IL
(2)
WP
X
V
V
/V
X
X
(1)
IH
IL
DD
I/O1
A13
A21
A29
A1
A9
Data Output
I/O0 - I/O7
Command
Data Input
Address
X
X
I/O0
A12
A20
A28
A0
A8