NAND04GW3B2AN1F NUMONYX [Numonyx B.V], NAND04GW3B2AN1F Datasheet - Page 32

• Manufacturer Part Number: NAND04GW3B2AN1F
• Description: 4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
• Manufacturer: NUMONYX [Numonyx B.V]

Data Protection
7
7.1
7.2
32/58
Data Protection
The device has both hardware and software features to protect against program and erase
operations.
It features a Write Protect, WP, pin, which can be used to protect the device against program
and erase operations. It is recommended to keep WP at V
down.
In addition, to protect the memory from any involuntary program/erase operations during
power-transitions, the device has an internal voltage detector which disables all functions
whenever V
The device features a Block Lock mode, which is enabled by setting the Power-Up Read
Enable, Lock/Unlock Enable, PRL, signal to High.
The Block Lock mode has two levels of software protection.
●
●
Refer to
mechanism.
Blocks Lock
All the blocks are locked simultaneously by issuing a Blocks Lock command (see
Commands).
All blocks are locked after power-up and when the Write Protect signal is Low.
Once all the blocks are locked, one sequence of consecutive blocks can be unlocked by
using the Blocks Unlock command.
Refer to
command.
Blocks Unlock
A sequence of consecutive locked blocks can be unlocked, to allow program or erase
operations, by issuing an Blocks Unlock command (see
The Blocks Unlock command consists of four steps:
●
●
●
●
The Start Block Address must be nearer the logical LSB (Least Significant Bit) than End
Block Address.
Blocks Lock/Unlock
Blocks Lock-down
One bus cycle to setup the command.
Three bus cycles to give the Start Block Address (refer to
and
One bus cycle to confirm the command.
Three bus cycles to give the End Block Address (refer to
and
Figure 16: Block Protection State Diagram
Figure 21: Command Latch AC Waveforms
Figure 14: Blocks Unlock
Figure 14: Blocks Unlock
DD
is below V
LKO
(see
Table 19: DC
Operation).
Operation).
Characteristics).
for an overview of the protection
for details on how to issue the
NAND04GW3B2B, NAND08GW3B2A
Table 7:
IL
during power-up and power-
Table 6: Address
Table 6: Address
Commands).
Definition,
Definition,
Table 7: