HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet
HYB18T512160AF
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HYB18T512160AF Summary of contents
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... HYB18T512400AF HYB18T512800AF HYB18T512160AF 512-Mbit DDR2 SDRAM DDR2 SDRAM RoHS Compliant Products Rev. 1. ...
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Edition 2005-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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... HYB18T512400AF HYB18T512800AF HYB18T512160AF 512-Mbit DDR2 SDRAM DDR2 SDRAM RoHS Compliant Products Rev. 1. ...
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5] Revision History: 2005-01 Previous Version: 2004-09 (Rev. 1.2) Page Subjects (major changes since last revision 113 Added , DS1 DH1 All Added 50 Ohm support All Document contains green products only Chapter 8 Pull-up and Pull-Down Driver ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.3 DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 High Performance DDR667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-400 & -533 112 Table 61 Derating Values for Data Setup and Hold Time of Single-ended DQS (DDR2-400 & -533 113 Table 62 Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 63 DDR2 Memory Components 116 Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM 8 Rev. 1.3, 2005-01 ...
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... Figure 51 Write with Auto-Precharge Example 1 ( Figure 52 Write with Auto-Precharge Example 2 (WR + Figure 53 Auto Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 4 I/O 4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 I/O 4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16 I/O 4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 t Limit Limit 512-Mbit DDR2 SDRAM t Limit ...
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List of Figures Figure 54 Self Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... DDR2–667C 4–4–4 f @CL5 333 CK5 f @CL4 333 CK4 f @CL3 200 CK3 t 12 RCD RAS HYB18T512400AF HYB18T512800AF HYB18T512160AF 1) –3S Unit DDR2–667D 5–5–5 — 333 MHz 266 MHz 200 MHz Rev. 1.3, 2005-01 09112003-SDM9-IQ3P ...
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Table 2 High Performance for DDR2–400B and DDR2–533C Product Type Speed Code Speed Grade max. Clock Frequency min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time 1.2 Description The 512-Mb DDR2 DRAM is a high-speed ...
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... HYB18T512400AF–3 4 DDR2–667 4–4–4 HYB18T512800AF–3 8 HYB18T512160AF–3 16 HYB18T512400AF–3S 4 HYB18T512800AF–3S 8 HYB18T512160AF– CAS: Column Adress Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge Note: For product nomenclature see Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/ CAS RCD ...
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... SSTL Chip Select Note: All command are masked when CS is registered HIGH. CS provides for external rank selection on systems with multiple memory ranks considered part of the command code. 14 512-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams 4. The abbreviations used in the Pin#/Buffer Rev ...
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... Activate commands and the column address and Auto- SSTL Precharge bit A10 (=AP) for Read/Write commands to SSTL select one location out of the memory array in the respective SSTL bank. A10(=AP) is sampled during a Precharge command SSTL to determine whether the Precharge applies to one bank SSTL (A10=LOW) or all banks (A10=HIGH) ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type G8 DQ0 I/O G2 DQ1 I/O H7 DQ2 I/O H3 DQ3 I/O H1 DQ4 I/O H9 DQ5 I/O F1 DQ6 I/O F9 DQ7 I/O C8 DQ8 I/O C2 DQ9 ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Data Mask 16 organization B3 UDM I F3 LDM I Power Supplies organizations V A9,C1,C3,C7, PWR DDQ PWR DD V ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Not Connected 16 organization A2, E2, L1, R3 R7, R8 Other Pins 4/ 8 organizations F9 ODT I Other Pins 16 organization K9 ODT I Table 5 ...
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TFBGA Ball Out Diagrams Figure 1 Pin Configuration for 4 components, P-TFBGA-60 (top view) Note and are power and ground for the DDL SSDL DLL.They are isolated on the device from ...
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Figure 2 Pin Configuration for 8 components, P-TFBGA-60 (top view) Note: 1. RDQS / RDQS are enabled by EMRS(1) command RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used ...
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Figure 3 Pin Configuration for 16 components, P-TFBGA-84 (top view) Note: 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] 2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for ...
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Mbit DDR2 Addressing Table 7 512 Mbit DDR2 Addressing Configuration 128 Bank Address BA[1:0] Number of Banks 4 Auto-Precharge A10 / AP Row Address A[13:0] Column Address A11, A[9:0] Number of Column 11 Address Bits ...
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... This Functional Block Diagram is intended to facilitate user understanding of the operation of the Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] Pin Configuration and Block Diagrams 4 I/O 4 Internal Memory Banks device; it does not represent an actual circuit implementation unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals ...
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... This Functional Block Diagram is intended to facilitate user understanding of the operation of the Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] Pin Configuration and Block Diagrams 8 I/O 4 Internal Memory Banks device; it does not represent an actual circuit implementation unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals ...
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... This Functional Block Diagram is intended to facilitate user understanding of the operation of the Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 16 I/O 4 Internal Memory Banks device; it does not represent an actual circuit implementation. 3. LDM, UDM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional LDQS and UDQS signals ...
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Functional Description 3.1 Simplified State Diagram Figure 7 Simplified State Diagram Note: This Simplified State Diagram is intended to provide a floorplan of the possible state transitions and the commands to control them. In particular situations involving more than ...
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Basic Functionality Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of ...
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... Power-Down mode, where the DLL is disabled. Address bit A13 and all “higher” address bits have to be set to 0 for compatibility with other DDR2 memory products with higher memory densities. 29 512-Mbit DDR2 SDRAM Functional Description ) ...
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Table 8 Mode Register Definition (BA[2:0] = 000B) 1) Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0 B BA1 15 Bank Address [ ...
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Table 8 Mode Register Definition (BA[2:0] = 000B) 1) Field Bits Type Description Burst Type [2:0] w Burst Length Note: All other bit combinations are illegal. 010 011 write ...
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Table 9 Extended Mode Register Definition (BA[2:0] = 001B) 1) Field Bits Type Description A13 13 w Address Bus[13] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0 B Qoff 12 Output Disable 0 B ...
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... EMRS(1). A13 and all “higher” address bits have to be set to 0 for compatibility with other DDR2 memory products with higher memory densities. Refer to Extended Mode Register Definition. Any time the DLL is reset, 200 clock cycles must occur ...
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Extended Mode Register EMR(2) The Extended Mode Registers EMR(2) and EMR(3) are reserved for future use and must be programmed when setting the mode register during initialization.The extended mode register EMR(2) is written by asserting LOW on CS, RAS, ...
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Extended Mode Register EMR(3) The Extended Mode Register EMR(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during Table 12 EMR(3) Programming Extended Mode Register ...
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Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before any other OCD Impedance ...
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Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMR(1) bit enabling ...
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For proper operation of adjust mode clocks and / should be met as shown Figure 10. Input data pattern for adjustment, DT[0:3] is fixed ...
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... EMRS(1) by address bit A10 = 0. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resis- tance for any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode ...
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ODT Truth Tables The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS(1) for all three device Table 15 ODT Truth Table Input Pin x4 ...
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ODT timing modes Depending on the operating mode asynchronous or synchronous ODT timings apply. t Asynchronous ODT timings ( AOFPD the on-die DLL is disabled. These modes are CK, CK CKE t IS ODT tAOND (2 tck) DQ ...
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CK, CK "low" CKE ODT tAONPD,min tAONPD,max Figure 14 ODT Timing for Precharge Power-Down and Active Power-Down Mode Note: Asynchronous ODT timings apply for Precharge Power-Down Mode and “Slow Exit” Active Power Down ...
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T-5 CK, CK CKE ODT turn-off, tANPD >= 3 tck : ODT ODT turn-off, tANPD <3 tck : ODT ODT turn-on, tANPD >= 3 tck : ODT ODT turn-on, tANPD < 3 tck : ODT Figure 15 ODT Mode Entry ...
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Mode exit As long as the timing parameter when ODT is turned on or off after exiting these power- down modes, synchronous timing parameters can CK CKE ODT turn-off, tAXPD >= tAXPDmin: Synchronous timings ...
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Bank Activate Command The Bank Activate command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the clock. The bank addresses BA[1:0] are used to select the desired bank. The ...
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... A single Read or Write Command will initiate a serial read or write operation on successive clock cycles at data rates 533 Mb/sec/pin for main memory. The boundary of the burst cycle is restricted to specific segments of the page length. For example, the 32 Mbit 4 I/O page length of 2048 bits (defined by CA[11, 9:0]) ...
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Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the bank ...
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CK, CK Activate CMD Bank A DQS, DQS tRCD DQ Figure 21 Read to Write Timing Example: Read followed by a write to the same bank t Activate to Read delay = : ...
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... Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst ...
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Read Command The Read command is initiated by having CS and CAS LOW while holding RAS and WE HIGH at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay ...
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CMD DQ's Figure 26 Read Operation Example ...
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CK, CK Posted CAS Posted CAS NOP CMD READ A READ B DQS, DQS Figure 28 Seamless Read Operation Example ...
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... The time from the completion of the burst write to bank precharge is named “write recovery time” and is the time needed to store the write data into WR the memory array. (see Chapter WR in the MRS DQSL ...
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CK, CK Posted CAS CMD NOP WRITE A DQS, DQS DIN A0 Figure 32 Write Operation Example ( 3 ...
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T0 T1 CK, CK Posted CAS CMD NOP WRITE A DQS, DQS Figure 34 Seamless Write Operation Example The seamless write operation ...
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... Data mask is not used during read cycles HIGH during a write burst coincident with the write data, the write data bit is not written to the memory. For function is disabled, when RDQS / RDQS are enabled by EMRS(1 ...
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Burst Interruption Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions Read Burst can only be interrupted by another Read ...
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Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are LOW and CAS is HIGH at the rising edge of the ...
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T0 T1 CK, CK CMD Posted CAS NOP READ BL/2 clks DQS, DQS >=tRAS first 4-bit prefetch Figure 41 Read Operation Followed by Precharge Example 2 RL ...
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T0 T1 CK, CK Posted CAS CMD NOP READ BL/2 clocks DQS, DQS >=tRAS Figure 43 Read Operation Followed by Precharge Example ( ...
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CK, CK Posted CAS CMD NOP WRITE A DQS, DQS Figure 45 Write followed by Precharge Example ( ...
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... The Precharge operation engaged by the Auto- Precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data access ...
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ste A10 ="high" BL ...
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ste A10 ="high" ...
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Write with Auto-Precharge If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically operation after the completion of the write burst plus the write recovery time delay (WR), ...
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Read or Write to Precharge Command Spacing Summary The following table summarizes the minimum command delays between Read, Read w/AP, Write, Write w/AP to the Precharge commands to the same banks and Precharge-All commands. Table 18 Minimum Command Delays ...
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Concurrent Auto-Precharge DDR2 devices support the Precharge” feature. A Read with Auto-Precharge enabled Write with Auto-Precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read ...
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CK, CK "high" CKE > CMD Figure 53 Auto Refresh Timing 3.24.2 Self-Refresh Command The Self-Refresh command can be used to retain data, even ...
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CK/CK CKE tis tAOFD ODT CMD Figure 54 Self Refresh Timing Note: 1. Device must be in the “All banks idle” state before entering Self Refresh mode 200 ) has to be satisfied ...
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Power-Down Entry Active Power-down mode can be entered after an Activate command. Precharge Power-down mode can be entered after a Precharge, Precharge-All or internal precharge command also allowed to enter power- mode after an Auto-Refresh command or MRS ...
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BL ...
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...
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Auto Refresh Figure 60 Auto-Refresh command to Power-Down entry MRS EMRS Figure 61 ...
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... DRAM requires CKE to be maintained HIGH for all valid operations as defined in this data sheet. If CKE asynchronously drops LOW during any valid operation, the DRAM is not guaranteed to preserve the contents of the memory array. If this event CKE drops low due to an ...
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Truth tables Table 20 Command Truth Table Function CKE Previous Cycle (Extended) Mode H Register Set Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single Bank Precharge H Precharge all Banks H Bank Activate H Write H Write with ...
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Table 21 Clock Enable (CKE) Truth Table for Synchronous Transitions 1) Current State CKE Previous Cycle (N-1) Power-Down L L Self Refresh L L Bank(s) H Active All Banks Idle H H Any State other H than listed above 1) ...
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AC & DC Operating Conditions 5.1 Absolute Maximum Ratings Table 23 Absolute Maximum Ratings Symbol Parameter V V Voltage on pin relative Voltage on pin relative to DDQ DDQ V V Voltage on pin ...
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DC Characteristics Table 25 Recommended DC Operating Conditions (SSTL_18) Symbol Parameter V Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF V Termination Voltage ...
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DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...
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Table 30 Differential DC and AC Input and Output Logic Levels Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID(ac differential cross point input IX(ac) voltage V ...
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Output Buffer Characteristics Table 31 SSTL_18 Output DC Current Drive Symbol Parameter I Output Minimum Source DC Current OH I Output Minimum Sink DC Current 1 1. DDQ OUT ...
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Full Strength Output V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS(1) bits A[9:7] =’111’. Figure 66 Table 34 Full Strength Default Pull-up Driver Characteristics Voltage (V) Pull-up Driver ...
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Figure 66 Full Strength Default Pull-up Driver Diagram Table 35 Full Strength Default Pull–down Driver Characteristics Voltage (V) Pull-down Driver Current [mA] 1) Min. 0.0 0.00 0.1 4.30 0.2 8.60 0.3 12.90 0.4 16.90 0.5 20.05 0.6 22.10 0.7 23.27 ...
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Figure 67 Full Strength Default Pull–down Driver Diagram 5.5.1 Calibrated Output Driver V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the Off-Chip Driver (OCD) Impedance Adjustment. The ...
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Table 36 Full Strength Calibrated Pull-down Driver Characteristics Voltage (V) Calibrated Pull-down Driver Current [mA] Nominal Minimum (21 Ohms) 0.2 9.5 0.3 14.3 0.4 18.7 1) The driver characteristics evaluation conditions are Nominal Minimum 95 ° The driver ...
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Reduced Output Drive Characteristics A driver mode with reduced output drive characteristics can be selected by setting address bit A1 in the EMRS(1) extended mode register to 1. Table 38 Reduced Strength Default Pull-up Driver Characteristics Voltage (V) Pull-up ...
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Figure 68 Reduced Strength Default Pull-up Driver Diagram Table 39 Reduced Strength Default Pull–down Driver Characteristics Voltage (V) Pull-down Driver Current [mA] 1) Min. 0.0 0.00 0.1 1.72 0.2 3.44 0.3 5.16 ...
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Figure 69 Reduced Strength Default Pull–down Driver Diagram 5.7 Input / Output Capacitance Table 40 Input ...
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Power & Ground Clamp V-I Characteristics Power and Ground clamps are provided on address (A[13:0], BA[11:0]), RAS, CAS, CS, WE, and ODT pins. Table 41 Power & Ground Clamp V-I Characteristics Voltage across clamp (V) 0.0 0.1 0.2 0.3 ...
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Figure 70 AC Overshoot / Undershoot Diagram for Address and Control Pins Table 43 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area 0.9 Maximum peak amplitude allowed for ...
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Currents Measurement Specifications and Conditions I Table 44 Measurement Conditions DD Parameter Operating Current - One bank Active - Precharge CK(IDD) RC RC(IDD) RAS commands. Address and control ...
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I Table 44 Measurement Conditions DD Parameter Self-Refresh Current CKE 0.2 V; external clock off, CK and Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current I 1. ...
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Table 46 I Specification for DDR2–667C and DDR2-667D DD Product Type Speed Code Speed Grade Symbol I DD0 I DD1 I DD2N I DD2P I DD2Q I DD3N I DD3P I DD4R I DD4W I DD5B I DD5D I DD6 ...
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Table 47 I Specification for DDR2–533C and DDR2–400B DD Product Type Speed Code Speed Grade Symbol I DD0 I DD1 I DD2N I DD2P I DD2Q I DD3N I DD3P I DD4R I DD4W I DD5B I DD5D I DD6 ...
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Test Conditions For testing the parameters, the following timing parameters are used Table 48 Measurement Test Conditions for DDR2–667C and DDR2–667D DD Parameter CAS Latency Clock Cycle Time Active to Read or Write delay ...
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On Die Termination (ODT) Current The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & the EMRS(1) a full or reduced termination can be selected. ...
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Electrical Characteristics 7.1 Speed Grade Defenitions Table 51 Speed Grade Definition Speed Bins for DDR667 Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active ...
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Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended ...
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Table 53 Timing Parameter by Speed Grade - DDR2-667 Parameter Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Read preamble Read postamble Active bank A to Active bank B ...
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MIN ( , ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i. this value can be greater than the minimum specification ...
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Table 54 Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK ...
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Table 54 Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont’d) Parameter Address and control input setup time DQ low-impedance time from DQS low-impedance from Mode register set command cycle time OCD drive ...
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Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings ...
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ODT AC Electrical Characteristics Table 55 ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD ...
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AC Timing Measurement Conditions 8.1 Reference Load for Timing Measurements Figure 72 represents the timing reference load used in defining the relevant timing parameters of the device not intended to either a precise representation of the typical ...
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Input and Data Setup and Hold Time 8.3.1 Definition for Input Setup ( Address and control input setup time ( from the input signal crossing at the V rising signal and for a falling signal applied to the IL(ac) ...
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Definition Data Setup ( t Data input setup time ( ) with single-ended data DS1 strobe enabled MR[bit10]=1, is referenced from the V input signal crossing at the IH(ac) V ended data strobe crossing IH/L(dc) transition for a rising ...
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Slew Rate Definition for Input and Data Setup and Hold Times t t Setup ( & ) nominal Slew Rate for a rising signal defined as the Slew Rate between the last crossing ...
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Figure 77 Slew Rate Definition Tangent Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM AC Timing Measurement Conditions 109 Rev. 1.3, 2005-01 09112003-SDM9-IQ3P ...
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Setup ( ) and Hold ( IS 1. For all input signals the total input setup time and input hold time required is calculated by adding the data sheet value to the derating value respectively. t Example: (total ...
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Table 58 Derating Values for Input Setup and Hold Time (DDR2-400 & DDR2-533) Command / Address Slew Rate (V/ns) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0 ...
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Table 59 Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-667) DQS, DQS Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ 2.0 +100 +45 +100 +45 ...
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Table 61 Derating Values for Data Setup and Hold Time of Single-ended DQS (DDR2-400 & -533) DQS, DQS Single-ended Slew Rate 2.0 V/ns 1.5 V/ns 1.0 V/ DS1 DH1 DS1 DH1 DS1 2.0 +188 +188 ...
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Package Dimensions Figure 78 Package Pinout PG-TFBGA-60 (top view) Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM 114 Package Dimensions Rev. 1.3, 2005-01 09112003-SDM9-IQ3P ...
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Figure 79 Package Pinout PG-TFBGA-84 (top view) Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM 115 Package Dimensions Rev. 1.3, 2005-01 09112003-SDM9-IQ3P ...
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... Product Namenclature Table 62 Nomenclature Fields and Examples Example for Field Number 1 2 DDR2 DRAM HYB 18 Table 63 DDR2 Memory Components Field Description 1 INFINEON Component Prefix 2 Interface Voltage [V] 3 DRAM Technology 4 Component Density [Mbit] 5+6 Number of I/Os 7 Product Variations 8 Die Revision 9 Package, Lead-Free Status ...
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Published by Infineon Technologies AG ...