HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 79

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

5.3
DDR2 SDRAM pin timing are specified for either single
ended or differential mode depending on the setting of
the EMRS(1) “Enable DQS” mode bit; timing
advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin
timing are measured is mode dependent. In single
ended mode, timing relationships are measured
Table 28
Symbol
V
V
V
V
Table 29
Symbol
V
V
SLEW
1) Input waveform timing is referenced to the input signal crossing through the
2) The input signal minimum Slew Rate is to be maintained over the range from
3) AC timings are referenced with input waveforms switching from
Figure 64
Data Sheet
IH(dc)
IL(dc)
IH(ac)
IL(ac)
REF
SWING.MAX
range from
on the negative transitions.
Parameter
DC input logic high
DC input low
AC input logic high
AC input low
DC & AC Characteristics
DC & AC Logic Input Levels
Single-ended AC Input Test Conditions
Single-ended AC Input Test Conditions Diagram
V
REF
V
Falling Slew =
SWING.MAX
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
to
V
IL(ac).MAX
Start of Falling Edge Input Timing
delta TF
for falling edges as shown in
V REF
delta TF
DDR2-400, DDR2-533
Min.
V
–0.3
V
—
REF
REF
- V IL (ac).MAX
+ 0.125
+ 0.250
Max.
V
V
—
V
DDQ
REF
REF
79
Start of Rising Edge Input Timing
Figure 64
relative to the rising or falling edges of DQS crossing at
V
are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is
verified by design and characterization but not subject
to production test. In single ended mode, the DQS (and
RDQS) signals are internally disabled and don’t care.
– 0.125
– 0.250
+ 0.3
REF
V
IL(ac)
delta TR
. In differential mode, these timing relationships
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
to
Rising Slew =
V
IH(ac)
DDR2-667
Min.
V
–0.3
V
—
REF
REF
V
on the positive transitions and
Value
0.5 x
1.0
1.0
V
REF
IH(ac).MIN
+ 0.125
+ 0.200
level applied to the device under test.
V IH(ac).MIN -
V
AC & DC Operating Conditions
DDQ
to
512-Mbit DDR2 SDRAM
V
delta TR
REF
Max.
V
V
—
V
V
DDQ
REF
REF
V
V
V
V
V
V
V
for rising edges and the
REF
DDQ
IH (ac) .MIN
IH (dc) .MIN
REF
IL (dc) .MAX
IL (ac) .MAX
SS
09112003-SDM9-IQ3P
– 0.125
– 0.200
+ 0.3
Unit
V
V
V / ns
Rev. 1.3, 2005-01
V
IH(ac)
Unit
V
V
V
V
Note
1)
1)
2)3)
to
V
IL(ac)