HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 14

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

2
The pin configuration of a DDR2 SDRAM is listed by function in
Type columns are explained in
depicted in Figure 1 for 4, Figure 2 for 8 and Figure 3 for 16
Table 4
Ball#/Pin#
Clock Signals 4/ 8 organizations
E8
F8
F2
Clock Signals 16 organization
J8
K8
K2
Control Signals 4/ 8 organizations
F7
G7
F3
G8
Data Sheet
Pin Configuration and Block Diagrams
Pin Configuration of DDR SDRAM
Name
CK
CK
CKE
CK
CK
CKE
RAS
CAS
WE
CS
Pin
Type
I
I
I
I
I
I
I
I
I
I
Table 5
SSTL
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
and
Table 6
Function
Clock Signal CK, Complementary Clock Signal CK
Note: CK and CK are differential system clock inputs. All address
Clock Enable
Note: CKE HIGH activates and CKE LOW deactivates internal
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Note: RAS, CAS and WE (along with CS) define the command
Chip Select
Note: All command are masked when CS is registered HIGH. CS
and control inputs are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossing of CK and CK (both
direction of crossing)
clock signals and device input buffers and output drivers.
Taking CKE LOW provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-
Down (row Active in any bank). CKE is synchronous for
power down entry and exit and for self-refresh entry. Input
buffers excluding CKE are disabled during self-refresh.
CKE is used asynchronously to detect self-refresh exit
condition. Self-refresh termination itself is synchronous.
After
initialisation sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh entry
and exit,
be maintained HIGH throughout read and write accesses.
Input buffers, excluding CK, CK, ODT and CKE are disabled
during power-down
being entered.
provides for external rank selection on systems with
multiple memory ranks. CS is considered part of the
command code.
respectively. The pin numbering for the FBGA package is
14
V
REF
V
Table
has become stable during power-on and
REF
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
must be maintained to this input. CKE must
4. The abbreviations used in the Pin#/Buffer
Pin Configuration and Block Diagrams
512-Mbit DDR2 SDRAM
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01