HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 52

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

Figure 28
RL = 5, AL = 2, CL = 3, BL = 4
The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
Figure 29
RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)
The seamless, non interrupting 8-bit read operation is supported by enabling a read command at every BL/2
number of clocks. This operation is allowed regardless of same or different banks as long as the banks are
activated.
Data Sheet
CK, CK
DQ
DQS,
DQS
CMD
DQS,
DQS
CK, CK
CMD
DQ
Posted CAS
READ A
T0
Posted CAS
READ A
T0
Seamless Read Operation Example 1
Seamless Read Operation Example 2
AL = 2
T1
NOP
T1
NOP
CL = 3
RL = 3
T2
Posted CAS
READ B
RL = 5
T2
NOP
CL = 3
T3
NOP
T3
NOP
Dout A0
Dout A1
T4
NOP
READ B
T4
Posted CAS
52
Dout A2
Dout A3
T5
NOP
Dout A0
T5
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
NOP
Dout A4
Dout A1
Dout A5
T6
NOP
Dout A2
T6
NOP
Dout A6
Dout A3
Dout A7
512-Mbit DDR2 SDRAM
T7
NOP
Dout B0
T7
NOP
Dout B0
Functional Description
09112003-SDM9-IQ3P
Dout B1
Dout B1
T8
Rev. 1.3, 2005-01
NOP
T8
Dout B2
NOP
Dout B2
SBR_BL8
Dout B3
SBR523
Dout B3
T9
NOP
Dout B4