HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 54

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

Figure 32
RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
Figure 33
RL = 5 (AL = 2, CL = 3), WL = 4,
The minimum number of clocks from the write command to the read command is (CL - 1) +BL/2 +
is the write-to-read turn-around time
the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
Data Sheet
DQS,
DQS
CK, CK
CMD
DQS,
DQS
DQ
CK, CK
CMD
DQ
Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6
Posted CAS
T0
WRITE A
T0
WL = RL - 1 = 4
NOP
Write Operation Example 2
Write followed by Read Example
WL = RL-1 = 2
T1
T1
NOP
NOP
DIN A0
DIN A0
T2
NOP
T2
t
WTR
NOP
<= t DQSS
t
WTR
DIN A1
DIN A1
= 2, BL = 4
expressed in clock cycles. The
DIN A2
DIN A2
T3
T3
NOP
NOP
DIN A3
DIN A3
T4
Posted CAS
T4
54
READ A
NOP
Completion of
the Burst Write
tWTR
AL=2
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
T5
T5
NOP
NOP
tWR
t
WTR
T6
T6
NOP
is not a write recovery time (
NOP
RL=5
512-Mbit DDR2 SDRAM
CL=3
Precharge
T7
T7
Functional Description
NOP
09112003-SDM9-IQ3P
tRP
Rev. 1.3, 2005-01
t
Bank A
Activate
WTR
T9
T8
NOP
, where
BW322
BWBR
t
WR
T9
) but
t
WTR