HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 33

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

A0 is used for DLL enable or disable. A1 is used for
enabling half-strength data-output driver. A2 and A6
enables On-Die termination (ODT) and sets the Rtt
value. A[5:3] are used for additive latency settings and
A[9:7] enables the OCD impedance adjustment mode.
A10 enables or disables the differential DQS and
RDQS signals, A11 disables or enables RDQS.
3.7
The DLL must be enabled for normal operation. DLL
enable is required during power up initialization, and
upon returning to normal operation after having the DLL
disabled. The DLL is automatically disabled when
entering Self-Refresh operation and is automatically re-
enabled and reset upon exit of Self-Refresh operation.
3.8
Under normal operation, the DRAM outputs are
enabled during Read operation for driving data (Qoff bit
in the EMR(1) is set to 0). When the Qoff bit is set to 1,
the DRAM outputs will be disabled. Disabling the
3.9
Table 10
RDQS, RQDS which can be programmed by A[11:10]
address bits in EMRS. RDQS and RDQS are available
Table 10
EMRS(1)
A11
(RDQS Enable)
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
Data Sheet
lists all possible combinations for DQS, DQS,
DLL Enable/Disable
Output Disable (Qoff)
Single-ended and Differential Data Strobe Signals
Single-ended and Differential Data Strobe Signals
A10
(DQS Enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
Strobe Function Matrix
RDQS/DM
DM
DM
RDQS
RDQS
RDQS
Hi-Z
Hi-Z
RDQS
Hi-Z
33
Address bit A12 have to be set to 0 for normal
operation. With A12 set to 1 the SDRAM outputs are
disabled and in Hi-Z. 1 on BA0 and 0 for BA1 have to
be set to access the EMRS(1). A13 and all “higher”
address bits have to be set to 0 for compatibility with
other DDR2 memory products with higher memory
densities. Refer to Extended Mode Register Definition.
Any time the DLL is reset, 200 clock cycles must occur
before a Read command can be issued to allow time for
the internal clock to be synchronized with the external
clock. Failing to wait for synchronization to occur may
result in a violation of the
DRAM outputs allows users to measure
during Read operations, without including the output
buffer current and external load currents.
in
components, the DM function is disabled. RDQS is
active for reads and don’t care for writes.
DQS
DQS
DQS
DQS
DQS
8 components only. If RDQS is enabled in
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
DQS
DQS
Hi-Z
DQS
Hi-Z
512-Mbit DDR2 SDRAM
Signaling
differential DQS signals
single-ended DQS signals
differential DQS signals
single-ended DQS signals
t
AC
or
Functional Description
09112003-SDM9-IQ3P
t
DQSCK
Rev. 1.3, 2005-01
parameters.
I
DD
currents
8