HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 38

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

For proper operation of adjust mode, WL = RL - 1 =
AL + CL - 1 clocks and
in
is fixed and not affected by MRS addressing mode (i.e.
Figure 10
Drive Mode
Both Drive(1) and Drive(0) are used for controllers to
measure DDR2 SDRAM Driver impedance before OCD
impedance adjustment. In this mode, all outputs are
Figure 11
Data Sheet
Figure
DQS_in
DQS_in
CK, CK
CMD
DQ_in
CK, CK
CMD
DQ_in
DM
10. Input data pattern for adjustment, DT[0:3]
EMRS(1)
EMRS(1)
Timing Diagram Adjust Mode
Timing Diagram Drive Mode
tOIT
Enter Drive Mode
OCD adjust mode
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0
WL
t
NOP
DS
NOP
/
t
DH
tDS tDH
should be met as shown
DT0
NOP
NOP
DQS high for Drive(1)
DQS high for Drive(0)
DT1
DQS
DT2
NOP
NOP
DT3
38
NOP
NOP
sequential or interleave). Burst length of 4 have to be
programmed in the MRS for OCD impedance
adjustment.
driven out
output drivers are turned-off
mode exit” command. See
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
EMRS(1)
NOP
tOIT
OCD calibration
t
OIT
OCD calibration
mode exit
tWR
after “enter drive mode” command and all
mode exit
NOP
NOP
512-Mbit DDR2 SDRAM
Figure
t
EMRS(1)
OIT
Functional Description
NOP
09112003-SDM9-IQ3P
after “OCD calibration
11.
Rev. 1.3, 2005-01
NOP
NOP
OCD1